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Summary: - Remove HSC OCP setting and use default setting(600W). Because 320W CPU is used currently, if we set HSC OCP to 350W it will trigger HSC CSOUT during power on. - Add ISR to record the following SEL to BMC. | sensor type | sensor number | event data | condition | |-------------|--------------------|-----------------------------|----------------------------------------------------------------------------------------------------| | C3h | 56h(POWER_ERROR) | 01FFFFh(SYS_PWROK_FAIL) | asserted when PWRGD_CPU_LVC3 is low and FM_CPU_BIC_SLP_S3_N is high. | | C9h | 10h(SYSTEM_STATUS) | 00FFFFh(SYS_THERMAL_TRIP) | asserted when FM_CPU_BIC_THERMTRIP_N falls | | C9h | 10h(SYSTEM_STATUS) | 02FFFFh(SYS_THROTTLE) | asserted/deassert when FM_CPU_BIC_PROCHOT_LVT3_N falls/rises | | C9h | 10h(SYSTEM_STATUS) | 05FFFFh(SYS_PMBUSALERT) | asserted/deassert when IRQ_HSC_ALERT1_N falls/rises | | C9h | 10h(SYSTEM_STATUS) | 06FFFFh(SYS_HSCTIMER) | asserted/deassert when FM_HSC_TIMER rises/falls | | C9h | 10h(SYSTEM_STATUS) | 07FFFFh(SYS_FIRMWAREASSERT) | asserted/deassert when FAST_PROCHOT_N falls/rises | | C9h | 10h(SYSTEM_STATUS) | 0AFFFFh(SYS_VRWATCHDOG) | asserted when PWRGD_CPU_LVC3 is low after FM_CPU_BIC_SLP_S3_N is high of 10 second. | | CBh | 71h(VR_OCP) | byte 1: VR number<br>0 - PVDDCR_CPU0<br> 1 - PVDDCR_CPU1<br>2 - PVDD11_S3 <br>byte 2: FFh<br>byte 3: FFh | asserted/deassert when PVDDCR_CPU0_BIC_OCP_N, PVDDCR_CPU1_BIC_OCP_N, PVDD11_S3_BIC_OCP_N fall/rise | | CBh | 72h(VR_ALERT) | byte 1: VR number and page<br>bit [7:1] - VR number<br>bit [0] - page<br>byte 2: VR STATUS_WORD byte 0<br>byte 3: VR STATUS_WORD byte 1 | asserted/deassert when PVDDCR_CPU0_PMALERT_N, PVDDCR_CPU1_PMALERT_N, PVDD11_S3_PMALERT_N fall/rise | | CCh | BDh(HDT_PRESENT) | FFFFFFh | asserted/deassert when FM_DBP_PRESENT_N falls/rises | Pull Request resolved: #488 Test Plan: Build code: Pass Reviewed By: williamspatrick Differential Revision: D38708679 Pulled By: GoldenBug fbshipit-source-id: 20950ba8ab263422df16165f7ee73fd04196db14
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