fby3.5: hd: Add ISR #488
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fby3.5: hd: Add ISR #488
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Summary: - Remove HSC OCP setting and use default setting(600W). Because 320W CPU is used currently, if we set HSC OCP to 350W it will triger HSC CSOUT during power on. - Add function to record the following SEL to BMC. sensor type , sensor number , event data , condition C3h , 56h(POWER_ERROR) , 01FFFFh(SYS_PWROK_FAIL) , asserted when PWRGD_CPU_LVC3 is low and FM_CPU_BIC_SLP_S3_N is high. C9h , 10h(SYSTEM_STATUS) , 00FFFFh(SYS_THERMAL_TRIP) , asserted when FM_CPU_BIC_THERMTRIP_N falls C9h , 10h(SYSTEM_STATUS) , 02FFFFh(SYS_THROTTLE) , asserted/deassert when FM_CPU_BIC_PROCHOT_LVT3_N falls/rises C9h , 10h(SYSTEM_STATUS) , 05FFFFh(SYS_PMBUSALERT) , asserted/deassert when IRQ_HSC_ALERT1_N falls/rises C9h , 10h(SYSTEM_STATUS) , 06FFFFh(SYS_HSCTIMER) , asserted/deassert when FM_HSC_TIMER rises/falls C9h , 10h(SYSTEM_STATUS) , 07FFFFh(SYS_FIRMWAREASSERT) , asserted/deassert when FAST_PROCHOT_N falls/rises C9h , 10h(SYSTEM_STATUS) , 0AFFFFh(SYS_VRWATCHDOG) , asserted when PWRGD_CPU_LVC3 is low after FM_CPU_BIC_SLP_S3_N is high of 10 second. CBh , 71h(VR_OCP) , byte 1: VR number , asserted/deassert when PVDDCR_CPU0_BIC_OCP_N, PVDDCR_CPU1_BIC_OCP_N, PVDD11_S3_BIC_OCP_N fall/rise 0 - PVDDCR_CPU0 1 - PVDDCR_CPU1 2 - PVDD11_S3 byte 2: FFh byte 3: FFh CBh , 72h(VR_ALERT) , byte 1: VR number and page , asserted/deassert when PVDDCR_CPU0_PMALERT_N, PVDDCR_CPU1_PMALERT_N, PVDD11_S3_PMALERT_N fall/rise bit [7:1] - VR number bit [0] - page byte 2: VR STATUS_WORD byte 0 byte 3: VR STATUS_WORD byte 1 CCh , BDh(HDT_PRESENT) , FFFFFFh , asserted/deassert when FM_DBP_PRESENT_N falls/rises Test Plan: Build code: Pass
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Aug 15, 2022
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Summary:
Because 320W CPU is used currently, if we set HSC OCP to 350W it will trigger HSC CSOUT during power on.
0 - PVDDCR_CPU0
1 - PVDDCR_CPU1
2 - PVDD11_S3
byte 2: FFh
byte 3: FFh
bit [7:1] - VR number
bit [0] - page
byte 2: VR STATUS_WORD byte 0
byte 3: VR STATUS_WORD byte 1
Test Plan:
Build code: Pass