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Signed-off-by: Matthew Ballance <matt.ballance@gmail.com>
fvutils · Sep 6, 2024 · f29be2d · f29be2d
1 parent 80b594c
commit f29be2d
Showing 1 changed file with 4 additions and 2 deletions.
diff --git a/src/pytest_fv/tool/hdl/sim/sim_vcs.py b/src/pytest_fv/tool/hdl/sim/sim_vcs.py
@@ -21,13 +21,15 @@
 #****************************************************************************
 import os
 import subprocess
-from pytest_fv import HdlSim, ToolRgy, ToolKind
+from pytest_fv import HdlSim, ToolRgy, ToolKind, FSConfig
 from .sim_vlog_base import SimVlogBase
 
 class SimVCS(SimVlogBase):
 
     def __init__(self, builddir):
-        super().__init__(builddir)
+        super().__init__(builddir, FSConfig({
+            "systemVerilogSource", "verilogSource"}, {
+                "sv-uvm": True}))
         pass
 
     def build(self):