…apic

…apic

Conflicts RESOLVED:
	src/platform/i386/hpet.c
	src/platform/i386/isr.h
	src/platform/i386/kernel.c
	src/platform/i386/kernel.h
	src/platform/i386/lapic.c
	src/platform/i386/vga.c
	src/platform/i386/vm.c

Ioapic api for multi-core and apicid programming

Multi-core in llbooter, capmgr, sl, cos_kernel_api(locks) and other related

* Major limitations: no kernel entry allowed at anytime. That could potentially
  screw up things for the "current thread".
* SCB and DCB are user-level only. Have to enable kernel-user page sharing, TODO!
* Given these limitations, tested sl_yield(), and the benchmarks look promising.
  With only kernel-level dispatching: AVG: 620, WC:804
  With only user-level dispatching: AVG: 340, WC: 750
  With shared pages, a couple more branches in the kernel-dispatching.

* TODO: API changes in capmgr for thread creation to pass in the address.
  My design is to let the users/schedulers decide the locality of a thread in
  a dcb region.
  * API changes obviously in the scheduling API, etc!
  * Most importantly, the kernel is not modified to detect an inconsistent state
  of an actual thread running vs the thread kernel thinks is running!
  And other checks for invocations etc!

* But the good news is, it works! Using the same heap allocation type API with no
special bump pointers or special capability type for SCB/DCB!

* TODO: use dcb capabilities instead of raw dcb pages

* TOKEN is only incremented on preemption.
* TODO: make sure the sched_tok accessed by the kernel is from SCB of
        a scheduling component.
* Clean up rcvcap sched_counter now! TODO!!

* Have SCB capability and resource working.
* TODO: DCB capabilities to work.
* TODO: Fix the API around SCB frontier.
* SCB address in a component will be the start of the heap pointer
  and the INIT DCB (initial dcb caps that are used when creating the
  INIT threads in those components) are next to SCB and statically set
  to be NUM_CPU number of pages. This is the idea to fix their addresses
  and avoid passing in component_information structure.

* Got SCB and DCB capabilities, api all plumbing working!!
* Some issues to debug, like asserts in my test for hierarchical
  scheduling. (without user-level dispatch!)

* TODO: with user-level dispatch, test in an "application" component
  using capmgr for dcb setup etc!

… update function

* TODO: cleanup sl_thd_yield functions that are there for debugging.
* TODO: uncomment sl_schedule side of functionality

* The pointers passed to the "SINV" call must be at least as small
  as the register sizes as the assembly for SINV writes registers
  back to those pointers.

* TODO: sl_thd_rcv() test!

* Fixed some multi-core stuff, need to be up to date with
  rump_cfe_integration branch where I've perhaps more bugs fixed!
* Added a OMP_HELLO program which is simple and just prints out HELLO.
* COS_GOMP really doesn't do anything multi-core for now!

* TODO: make the cos_gomp bookkeep for each "TEAM" and also enable
        cross-core execution!

…nto ppos

* Plus, modified serial baudrate to 115200kbps

* NOTE: include changes in ps library also!

 into ppos

Resoved conflicts, now, time to test functionality!

- blockpoints added, along with a simple lock on top
- added blkpts to sl to support the blkpt library
- added a stacklist for stack-allocated block-tracking structures

Note that this is currently NOT multi-core safe as it relies on the sl
critical section. Will need to change the stacklist to track trebor
stacks of threads to work for multi-core.

…acking

- Simply used a Treiber Stack (CAS-driven stack) that doesn't have ABA
  problems given the blocking behavior of threads.
- Remaining problem: we don't use `sl`'s support to wake threads
  across cores.

* with usage in cos_gomp
* TODO: pretty much everything!

…ched

- Asynchronous by default, and blocking on boundary conditions (queue full/empty)
- Macros to inline most of the channel logic and enable the magic of constant propagation
- Simple implementation for a single producer, single consumer

* sl_mod_part_fifo tracks a single idle thread per core which is
scheduled when there is nothing else on that core to run.

* BIG TODO: Test it's working!

* This is to avoid locks in common case.
* inner parallel structs will use stack for part_task but they're
  not going to be added into the main list as they're going to
  be run by the master thread

line.

* But I didn't fix INIT caps and I didn't test any of it in the last commit.
* per-core caps have to be on seperate cache lines, now, with thread
migration and reuse of a capability, changed thread to use a full cache
line.
* initthd, inittcap both occupy 64B cacheline.
* For the other caps, cos_kernel_api does size based and core-based
frontiers, so we're good.

* Trade off: If a thread is migrated across multiple cores, and if we
  freshly create per-core capability slot on each migration, we'd
probably be wasting a lot of space especially if we don't use that
core-local capability.
  In this simple(??) design though, we use a single capability that is as
big as a cache line and modify coreid on it to make it a core-local for
migrated core.

* idea is, if we're the only thread on the current core and
  we're yielding: it just means we're at a barrier or some sync
  point. So let's just try and run the idle thread which will
  wakeup other thread.
  Thread that wakes up, tries work and if there is none, will block
  again waiting to be woken up by the idle thread!

This macro should be in a separate header and part of git-ignore so
we don't need to commit this file for our changes.

* everything else uses non-timeout fast-user-dispatch api

…ched

or on expiry

* i had previously changed it to multi-core cas for some debugging,
  forgot to revert back.

* using cross-core asnds for wakeup results in general-protection fault.
  TODO: debug and fix that.

THIS DOES NOT SOLVE THE PROBLEM WITH IPIs I'VE RIGHT NOW

* ps_slab usage has problems, i couldn't get it to work correctly.
  will get to that eventually.
* STILL NO CLUE ON THE IPI PREEMPTION PROBLEM, just pushing the
  current working code without IPIs.