Units(SystemVerilog): add test for void function

cf. universal-ctags#2703

Units/parser-verilog.r/systemverilog-task-function.d/expected.tags

@@ -7,6 +7,14 @@ attr	input.sv	/^  task automatic attr ( (* my_attr *) const ref foo, enum { s0,
 foo	input.sv	/^  task automatic attr ( (* my_attr *) const ref foo, enum { s0, s1 } sel_e );$/;"	p	task:task_func.attr
 sel_e	input.sv	/^  task automatic attr ( (* my_attr *) const ref foo, enum { s0, s1 } sel_e );$/;"	p	task:task_func.attr
 C	input.sv	/^class C;$/;"	C
+M	input.sv	/^module M (output a, input b, c, d);$/;"	m
+a	input.sv	/^module M (output a, input b, c, d);$/;"	p	module:M
+b	input.sv	/^module M (output a, input b, c, d);$/;"	p	module:M
+c	input.sv	/^module M (output a, input b, c, d);$/;"	p	module:M
+d	input.sv	/^module M (output a, input b, c, d);$/;"	p	module:M
+myprint	input.sv	/^  function void myprint (int a);$/;"	f	module:M
+a	input.sv	/^  function void myprint (int a);$/;"	p	function:M.myprint
+x	input.sv	/^    logic x;$/;"	r	function:M.myprint
 foo	input.sv	/^package foo;$/;"	K
 uvm_object	input.sv	/^  typedef logic uvm_object;$/;"	T	package:foo
 bar	input.sv	/^  function logic bar (uvm_object baz);$/;"	f	package:foo

Units/parser-verilog.r/systemverilog-task-function.d/input.sv

@@ -24,6 +24,18 @@ class C;
   typedef class   fwd_type_class;
 endclass
 
+// LRM 13.4.1 Return values and void functions
+module M (output a, input b, c, d);
+  always_comb begin
+    a = b + myfunc1(c, d); // call myfunc1 (defined above) as an expression
+    myprint(a); // call myprint (defined below) as a statement
+  end
+
+  function void myprint (int a);
+    logic x;
+  endfunction
+endmodule
+
 // from UVM-1.2
 package foo;
   import "DPI-C" context function int import_func (string str);