verilog: keep trace with instance in TAGS file #2703

my2817 · 2020-11-18T06:52:08Z

add a kind named K_INST
update function tagNameList to update kind from K_IDENTIFIER to K_INST

masatake · 2020-11-18T10:58:47Z

The way to write test cases is wrong. expected.tags is missing. See https://docs.ctags.io/en/latest/units.html.
You should not use _ as the part of the kind name. The tests on the CI environment may be failed because of the _ in the kind name.

hirooih · 2020-11-18T23:51:51Z

Thanks for enhancement.

Please use terminology used in the LRM (Language Reference Manual), inst -> instance.
Verilog does not support interface.
Please check with the following tests.

make units LANGUAGES=SystemVerilog,Verilog
make units LANGUAGES=SystemVerilog,Verilog VG=1

Make sure only instance names are tagged.

hirooih · 2020-11-18T23:59:41Z

Make sure only instance names are tagged.

And;

Make sure all instance names are tagged.

my2817 · 2020-11-19T00:12:40Z

Make sure only instance names are tagged.

And;

Make sure all instance names are tagged.

Thanks for your work on this awesome tool and advice.

masatake · 2020-11-19T03:15:17Z

parsers/verilog.c

 		{
+			if(c == '('){


we don't use this style, putting { at the end of line IN THIS FILE.

if (c == '(') { ...

is expected.

parsers/verilog.c

codecov · 2020-11-19T03:16:34Z

Codecov Report

Merging #2703 (05f5707) into master (5938fa1) will increase coverage by 0.00%.
The diff coverage is 100.00%.

@@           Coverage Diff           @@
##           master    #2703   +/-   ##
=======================================
  Coverage   86.99%   86.99%           
=======================================
  Files         185      185           
  Lines       39462    39465    +3     
=======================================
+ Hits        34330    34334    +4     
+ Misses       5132     5131    -1

Impacted Files	Coverage Δ
parsers/verilog.c	`98.75% <100.00%> (+<0.01%)`	⬆️
main/kind.c	`98.29% <0.00%> (+0.34%)`	⬆️

Continue to review full report at Codecov.

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Δ = absolute <relative> (impact), ø = not affected, ? = missing data
Powered by Codecov. Last update 5938fa1...05f5707. Read the comment docs.

masatake · 2020-11-19T03:17:16Z

parsers/verilog.c

+							token->kind = K_UNDEFINED;
+							kind = K_UNDEFINED;
+					}
+					else {


we don't use this style, putting { at the end of line IN THIS FILE.

else
{
...

is expected.

masatake · 2020-11-19T03:21:13Z

parsers/verilog.c

+							kind = K_UNDEFINED;
+					}
+					else {
+							verbose("find instance: %s with kind %d\n", vStringValue (token->name), token->kind);


How about printing the kind in a string?

verbose("find instance: %s with kind %s\n", vStringValue (token->name),getNameForKind(token->kind));

(I myself didn't test the change that I showed.)

masatake · 2020-11-19T03:31:28Z

I would like you to squash the commits into one commit.
The idea behind the squashing is described in #2705 (comment) .

In addition, I would like you to use "SystemVerilog" or "Verilog,SystemVerilog" instead of "[verilog/SystemVerilog]" as the prefix of the commit header like:

cc26cc1d Ruby: fill signature fields for the method kind
65f5bc5b Go: use symbol table for attaching typeref field to members of a structure
bf1206cc SystemVerilog: parse a multi dimensional packed array in typedef correctly

masatake · 2020-11-19T21:24:06Z

parsers/verilog.c

+				token->kind = K_INSTANCE;
+				kind = K_INSTANCE;
+				c = skipPastMatch ("()");
+				if(c != ';' && c != ',')


We can simplify the code a bit like:

if (c == '(') { kind = K_UNDEFINED; c = skipPastMatch ("()"); if (c == ';' || c == ',') { kind = K_INSTANCE; verbose("find instance: %s with kind %s\n", vStringValue (token->name), getNameForKind(kind)); } token->kind = kind; }

I will check this code in detail in this week.
Quick comments.

I propose the followings;

if (c == '(') { c = skipPastMatch ("()"); if (c == ';' || c == ',') { kind = K_INSTANCE; verbose("find instance: %s with kind %s\n", vStringValue (token->name), getNameForKind(kind)); } else // comment why this condition is required kind = K_UNDEFINED; token->kind = kind; }

Actually I don't understand why the condition is required.

From LRM 23.3.2 Module instantiation syntax

module_instantiation ::= // from A.4.1.1 module_identifier [ parameter_value_assignment ] hierarchical_instance { , hierarchical_instance }; ... hierarchical_instance ::= name_of_instance ( [ list_of_port_connections ] ) name_of_instance ::= instance_identifier { unpacked_dimension } ...

Please take care of { unpacked_dimension } part.

Please check interface instantiation syntax, too.

From the units test, the parser will treat "`add_t" as instance if there isn't a "else" condition

var `add_t(foo) = '0;

I will check unpacked_dimension and interface syntax later, thanks.

coveralls · 2020-11-20T10:40:57Z

Coverage increased (+0.003%) to 87.087% when pulling 05f5707 on my2817:verilog_TagInst into 5938fa1 on universal-ctags:master.

hirooih

Thank you for your proposal.

Instance name support is very important. I completely missed the issue.
Please see my comments.

There is one issue. If I understand your fix correctly, it tags a void function as a instance.

// LRM 13.4.1 Return values and void functions
myprint(a); // call myprint (defined below) as a statement
function void myprint (int a);  // FIXME
...
endfunction

Void function is not used often. Supporting instance tag is much more important. Leave it as known bug for now.

Please add the test case above, too.

Thanks.

hirooih · 2020-11-20T12:58:29Z

parsers/verilog.c

@@ -1577,8 +1580,26 @@ static int tagNameList (tokenInfo* token, int c)
 	{
 		c = processType(token, c, &kind);	// update token and kind

-		if (c == '=' || c == ',' || c == ';' || c == ')' || c == '`')
+		if (c == '=' || c == ',' || c == ';' || c == ')' || c == '`' || c == '(' || c == '[')


Instance processing is dependent from variable processing. The following structure is more readable.

if (c == '=' || c == ',' || c == ';' || c == ')' || c == '`') { ... } else if (c == '(' ...) ...

hirooih · 2020-11-20T12:58:42Z

parsers/verilog.c

 		{
+			while(c == '[')
+			{
+				c = skipPastMatch ("[]");


You can use skipDimension().

hirooih · 2020-11-20T13:07:06Z

parsers/verilog.c

+			}
+			if(c == '(')
+			{
+				c = skipPastMatch ("()");


We need c= skipWhite (c); here.

m inst () ; // a space before semicolon fails. (You may want to add a test case for this. )

skipPastMatch() should do the job, but it does not now. I will work on this issue on this weekend.
You may wait for the fix.

hirooih · 2020-11-20T13:08:26Z

parsers/verilog.c

@@ -127,7 +128,8 @@ static kindDefinition VerilogKinds [] = {
 { true, 'p', "port",      "ports" },
 { true, 'r', "register",  "variable data types" },
 { true, 't', "task",      "tasks" },
- { true, 'b', "block",     "blocks (begin, fork)" }
+ { true, 'b', "block",     "blocks (begin, fork)" },
+ { true, 'i', "instance",  "instance(module instance)" }


Please be consistent with the line above. i.e. "instance (module, instance)"

hirooih · 2020-11-20T13:08:34Z

parsers/verilog.c

@@ -140,6 +142,7 @@ static kindDefinition SystemVerilogKinds [] = {
 { true, 'r', "register",  "variable data types" },
 { true, 't', "task",      "tasks" },
 { true, 'b', "block",     "blocks (begin, fork)" },
+ { true, 'i', "instance"   "instance(module or interface instance)"},


hirooih

Sorry for many change requests...

hirooih · 2020-11-21T02:02:26Z

parsers/verilog.c

@@ -1577,13 +1580,32 @@ static int tagNameList (tokenInfo* token, int c)
 	{
 		c = processType(token, c, &kind);	// update token and kind

-		if (c == '=' || c == ',' || c == ';' || c == ')' || c == '`')
+		if (c == '=' || c == ',' || c == ';' || c == ')' || c == '`' )


Remove a space you added.

hirooih · 2020-11-21T02:03:22Z

parsers/verilog.c

+					createTag (token, kind);
+				}
+				else
+				{


This else clause is not necessary.

hirooih · 2020-11-21T02:07:14Z

parsers/verilog.c

+		else if (c == '(' || c == '[') // should be instance? TODO: function void foo();
+		{
+			c = skipDimension(c);
+			if(c == '(')


This if-clause is not necessary.

hirooih · 2020-11-21T02:10:34Z

parsers/verilog.c

+				/* c= skipWhite (c); */
+				if(c == ';' || c == ',')
+				{
+					kind = K_INSTANCE;


This variable is not necessary.

OK, I'm sorry for my poor coding skill 😭

hirooih · 2020-11-21T02:11:45Z

parsers/verilog.c

+		else if (c == '(' || c == '[') // should be instance? TODO: function void foo();
+		{
+			c = skipDimension(c);
+			if(c == '(')


add a space after 'if'.

hirooih · 2020-11-21T02:13:32Z

parsers/verilog.c

@@ -127,7 +128,8 @@ static kindDefinition VerilogKinds [] = {
 { true, 'p', "port",      "ports" },
 { true, 'r', "register",  "variable data types" },
 { true, 't', "task",      "tasks" },
- { true, 'b', "block",     "blocks (begin, fork)" }
+ { true, 'b', "block",     "blocks (begin, fork)" },
+ { true, 'i', "instance",  "instances" }


If you chose "instances of module or interface" below, this should be "instances of module".

hirooih · 2020-11-21T02:14:02Z

parsers/verilog.c

@@ -140,6 +142,7 @@ static kindDefinition SystemVerilogKinds [] = {
 { true, 'r', "register",  "variable data types" },
 { true, 't', "task",      "tasks" },
 { true, 'b', "block",     "blocks (begin, fork)" },
+ { true, 'i', "instance"   "instances of module or interface"},


Add a space before "}".

hirooih

It is getting simpler, isn't it?

hirooih · 2020-11-21T04:58:30Z

parsers/verilog.c

+			c = skipDimension(c);
+			c = skipPastMatch ("()");
+			c = skipWhite (c);
+			if (c == ';' || c == ',')


Leave a comment here as we discussed.

hirooih · 2020-11-21T05:01:16Z

parsers/verilog.c

+			c = skipWhite (c);
+			if (c == ';' || c == ',')
+			{
+				kind = K_INSTANCE;


It seems that you missed my review comment this morning.
This variable is not necessary. You can specify K_INSTANCE directly.

Get it, thanks!

hirooih · 2020-11-21T05:06:32Z

parsers/verilog.c

+		{
+			c = skipDimension(c);
+			c = skipPastMatch ("()");
+			c = skipWhite (c);


I've sent a pull-request #2718 for this. I am waiting for the approval by @masatake.
If it is merged earlier than this pull-request, remove this line.

Again add a test case which fails by this issue. (Add a space in ");" at the end of one of module instantiations.)

hirooih

See my comment.

Again add a test case which fails by this issue. (Add a space in ");" at the end of one of module instantiations.)

For example;
verilog-instance.d/input.v: L57

             .b                         (b));

Change this line as;

             .b                         (b))   ;  // spaces before semicolon

Remove;

			c = skipWhite (c);

and confirm that the test fails.

And #2718 is merged into universal-ctags:master.
Merge it into your branch and confirm the test passes.

hirooih · 2020-11-21T12:27:22Z

parsers/verilog.c

+			// var `add_t(foo) = '0;
+			if (c == ';' || c == ',')
+			{
+				verbose("find instance: %s with kind %s\n", vStringValue (token->name), getNameForKind(kind));


kind is in this line, too.

hirooih · 2020-11-21T12:46:08Z

One more thing.
Have you checked the coverage report? (It is a really awesome tool.)

https://codecov.io/gh/universal-ctags/ctags/compare/4a9f00a1c199133729819043292aedff7c580ed8...2069733b92a881ec74bd5419d186611e7432e870/changes

Your fix made the following lines unnecessary.

1643 | 1660 |   | /* skip port list of module instance: foo bar(xx, yy); */
1644 | 1661 |   | c = skipWhite (c);
1645 | 1662 |   | if (c == '(')
1646 | 1663 |   | {
1647 | 1664 |   | c = skipPastMatch ("()");
1648 | 1665 |   | c = skipWhite (c);
1649 | 1666 |   | }

Please remove them.

Your fix added very small number of lines and gave us great functionality. It sounds great!

SystemVerilog: give K_INSTANCE to createTag directly SystemVerilog: new test case Add a space in ");" at the end of one of module instantiationsadd

hirooih · 2020-11-22T05:33:52Z

Again, thank you for your contribution.

my2817 · 2020-11-22T05:45:33Z

Again, thank you for your contribution.

Thanks for your patience!

masatake · 2020-11-22T19:24:44Z

I'm working on VHDL and I have studied some concepts of this technology area.
I got some ideas to improve SystemVerilog parser.

module foo # (parameter
...
endmodule: foo
...

  foo uut7 [1:0][10:0]();

for uut7, ctags with this pull request emits:

uut7   input.v /^   foo uut7 [1:0][10:0]();$/;"        i       module:top

I think we can fill typeref: field for representing the relationship between uut7 and foo.

uut7   input.v /^   foo uut7 [1:0][10:0]();$/;"        i       module:top       typeref:module:foo

I'm taking the same approach in VHDL.

hirooih · 2020-11-23T00:03:56Z

Thanks.
I've added the feature on the TODO list #2674 .

cf. universal-ctags#2703

masatake assigned hirooih Nov 18, 2020

my2817 closed this Nov 19, 2020

my2817 reopened this Nov 19, 2020

masatake reviewed Nov 19, 2020

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my2817 changed the title ~~[verilog/SystemVerilog] keep trace with instance in TAGS file~~ verilog: keep trace with instance in TAGS file Nov 19, 2020

masatake reviewed Nov 19, 2020

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hirooih requested changes Nov 20, 2020

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hirooih mentioned this pull request Nov 21, 2020

SystemVerilog,refactor: call skipWhite() at the end of skipPastMatch() #2718

Merged

hirooih requested changes Nov 21, 2020

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SystemVerilog: find instance, more readable

05f5707

SystemVerilog: give K_INSTANCE to createTag directly SystemVerilog: new test case Add a space in ");" at the end of one of module instantiationsadd

hirooih approved these changes Nov 22, 2020

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hirooih merged commit bdeb61a into universal-ctags:master Nov 22, 2020

hirooih mentioned this pull request Nov 22, 2020

Verilog/SystemVerilog Parser TODO List #2674

Open

38 tasks

hirooih added a commit to hirooih/ctags that referenced this pull request Dec 4, 2020

Units(SystemVerilog): add test for void function

49b9d23

cf. universal-ctags#2703

hirooih mentioned this pull request Dec 19, 2020

SystemVerilog: fix ctags --list-kinds-full=SystemVerilog listing #2766

Merged

hirooih mentioned this pull request Aug 26, 2022

Verilog: create tag of instance's reference name #3469

Closed

verilog: keep trace with instance in TAGS file #2703

verilog: keep trace with instance in TAGS file #2703

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