Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

verilog: keep trace with instance in TAGS file #2703

Merged
merged 1 commit into from
Nov 22, 2020
Merged

verilog: keep trace with instance in TAGS file #2703

merged 1 commit into from
Nov 22, 2020

Commits on Nov 22, 2020

  1. SystemVerilog: find instance, more readable

    SystemVerilog: give K_INSTANCE to createTag directly
    SystemVerilog: new test case
    Add a space in ");" at the end of one of module instantiationsadd
    my2817 committed Nov 22, 2020
    Configuration menu
    Copy the full SHA
    05f5707 View commit details
    Browse the repository at this point in the history