Strict Mode

Some of the strict rules of systemRDL seem a bit odd. By default, peakRDL-verilog will implement "sensible" behaviour when properties are not explicitly defined. This can be overridden by explicitly defining a property or putting the exporter into strict mode. Below is all the properties that have non-srict behaviour.

we

when not defined the property has the following default values:

True - when field is hw writeable, implements storage and is not sitcky False - in all other situations

this means HW writeable fields will have an external port name _we by default. This field will not be present for wires (HW=w, SW=r) or interrupt fields.