Validation-Microcontroller-CPU-SystemVerilog

A fully automated testbench for microcontroller CPU CISC

Name		Name	Last commit message	Last commit date
Latest commit History 10 Commits
block-diagram		block-diagram
ALU.vhd		ALU.vhd
LICENSE		LICENSE
README.md		README.md
SV_RAND_CHECK.sv		SV_RAND_CHECK.sv
cpu.vhd		cpu.vhd
datapath.vhd		datapath.vhd
instr_package.sv		instr_package.sv
mem_class.sv		mem_class.sv
memory.sv		memory.sv
micro_assembly_code.vhd		micro_assembly_code.vhd
microcode_fsm.vhd		microcode_fsm.vhd
register_file.vhd		register_file.vhd
tcl_stacktrace.txt		tcl_stacktrace.txt
test_cpu_advanced.vhd		test_cpu_advanced.vhd
top.sv		top.sv
top.sv.bak		top.sv.bak
vsim.wlf		vsim.wlf

Provide feedback