[SYCL][Doc] Deploy documentation for PI #1318
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Signed-off-by: Alexander Batashev <alexander.batashev@intel.com>
bader
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Mar 14, 2020
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…e_api_test * origin/sycl: (1188 commits) [SYCL][CUDA] Improve CUDA backend documentation (intel#1293) [SYCL] Emit textual IR when -S -fsycl-device-only is used (intel#1314) [SYCL] Add prototype of group algorithms (intel#1236) [SYCL] XFAIL test on windows to unblock pulldown Allow Intel Loop Controls only with SPV_INTEL_fpga_loop_controls Apply suggested assert msg change Implement SPV_INTEL_io_pipes extension [SYCL] Fix dependencies for SYCLLowerIR (intel#1321) [CI] Allow builds without pre-downloaded OpenCL in configure.py (intel#1317) [SYCL] Move SYCL headers from standard clang location (intel#1308) [mlir] Add support for generating dialect declarations via tablegen. Be more strict when checking existence of foo [CodeGenPrepare] Freeze condition when transforming select to br [ORC] Remove an undefined static method from LLJIT. [JITLink][AArch64] Fix incorrect capitalization in a testcase name. [ORC] Print symbol flags and materializer name in ExecutionSession::dump. [JITLink][MachO] Re-apply b64afad, MachO linker-private support, with fixes. Basic Block Sections Support. Test commit. [SYCL][Doc] Deploy documentation for PI (intel#1318) ...
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Previous register encoding assumed that the register index to encoded value mapping for every register class is contiguous. However, some newly added register class has non-contiguous assignments so these classes were handled exceptionally with linear search to find its decoded value (see intel#1318). This refactoring includes: - Defines modular register class decoding classes that can be assigned to each base register class, which includes Ascending, Descending, and table-based decoding classes. - At decoder initialization decoding classes are mapped to each base register class and table initialization is done for table-based classes. - Decoding/enforcing verification is done for debug build, e.g. check the decoding/encoding range in contiguously mapped for ascending/descending classes. - Refactors base register class mapping structure to a more intuitive map type.
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Signed-off-by: Alexander Batashev alexander.batashev@intel.com