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[FIRRTL] Add parser support for flow
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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seldridge committed Apr 30, 2021
1 parent 5752a78 commit 2893871
Showing 1 changed file with 7 additions and 2 deletions.
9 changes: 7 additions & 2 deletions lib/Dialect/FIRRTL/Import/FIRParser.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2556,12 +2556,14 @@ ParseResult FIRStmtParser::parseWire() {
parseToken(FIRToken::colon, "expected ':' in wire") ||
parseType(type, "expected wire type") || parseOptionalInfo(info))
return failure();
type = DuplexFlow::get(type);

ArrayAttr annotations = getState().emptyArrayAttr;
getAnnotations(getModuleTarget() + ">" + id, annotations);
auto name = hasDontTouch(annotations) ? id : filterUselessName(id);

auto result = builder.create<WireOp>(info.getLoc(), type, name, annotations);
auto result = builder.create<WireOp>(info.getLoc(), type,
name, annotations);
return addSymbolEntry(id, result, info.getFIRLoc());
}

Expand Down Expand Up @@ -2597,6 +2599,7 @@ ParseResult FIRStmtParser::parseRegister(unsigned regIndent) {
parseExp(clock, subOps, "expected expression for register clock"))
return failure();
clock = convertToPassive(clock, clock.getLoc());
type = DuplexFlow::get(type);

// Parse the 'with' specifier if present.
Value resetSignal, resetValue;
Expand Down Expand Up @@ -2740,7 +2743,9 @@ FIRModuleParser::parsePortList(SmallVectorImpl<PortInfoAndLoc> &result,

// If this is an output port, flip the type.
if (isOutput)
type = FlipType::get(type);
type = SinkFlow::get(type);
else
type = SourceFlow::get(type);

// FIXME: We should persist the info loc into the IR, not just the name
// and type.
Expand Down

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