[LLHD] Align signals with other wire/variable ops

Make the `llhd.sig` op use the same naming pattern as HW wires, Moore
variables, Seq registers, and a handful of other operations in CIRCT.
These all use the `custom<ImplicitSSAName>` parser to provide uniform
handling of optional names.

Make the signal name optional to align with other ops.

Rename the class to `SignalOp` for clarity.

include/circt/Dialect/LLHD/IR/LLHDSignalOps.td

@@ -11,12 +11,14 @@
 //===----------------------------------------------------------------------===//
 
 include "mlir/IR/EnumAttr.td"
-
-def SigOp : LLHDOp<"sig", [
-    TypesMatchWith<
-      "type of 'init' and underlying type of 'signal' have to match.",
-      "init", "result", "hw::InOutType::get($_self)">
-  ]> {
+include "mlir/IR/OpAsmInterface.td"
+
+def SignalOp : LLHDOp<"sig", [
+  DeclareOpInterfaceMethods<OpAsmOpInterface, ["getAsmResultNames"]>,
+  TypesMatchWith<
+    "type of 'init' and underlying type of 'signal' have to match.",
+    "init", "result", "hw::InOutType::get($_self)">
+]> {
   let summary = "Create a signal.";
   let description = [{
     The `llhd.sig` instruction introduces a new signal in the IR. The input
@@ -28,17 +30,22 @@ def SigOp : LLHDOp<"sig", [
 
     ```mlir
     %c123_i64 = hw.constant 123 : i64
-    %sig_i64 = llhd.sig "foo" %c123_i64 : i64
+    %foo = llhd.sig %c123_i64 : i64
+    %0 = llhd.sig name "foo" %c123_i64 : i64
     ```
 
     This example creates a new signal named "foo", carrying an `i64` type with
     initial value of 123.
   }];
-
-  let arguments = (ins StrAttr: $name, HWValueType: $init);
-  let results = (outs InOutType: $result);
-
-  let assemblyFormat = "$name $init attr-dict `:` qualified(type($init))";
+  let arguments = (ins
+    OptionalAttr<StrAttr>:$name,
+    HWValueType:$init
+  );
+  let results = (outs Res<InOutType, "", [MemAlloc]>:$result);
+  let assemblyFormat = [{
+    `` custom<ImplicitSSAName>($name) $init attr-dict
+    `:` type($init)
+  }];
 }
 
 def PrbOp : LLHDOp<"prb", [

lib/Conversion/MooreToCore/MooreToCore.cpp

@@ -337,8 +337,8 @@ struct VariableOpConversion : public OpConversionPattern<VariableOp> {
       init = rewriter.createOrFold<hw::BitcastOp>(loc, elementType, constZero);
     }
 
-    rewriter.replaceOpWithNewOp<llhd::SigOp>(op, resultType, op.getNameAttr(),
-                                             init);
+    rewriter.replaceOpWithNewOp<llhd::SignalOp>(op, resultType,
+                                                op.getNameAttr(), init);
     return success();
   }
 };

lib/Dialect/LLHD/IR/LLHDOps.cpp

@@ -12,6 +12,7 @@
 
 #include "circt/Dialect/LLHD/IR/LLHDOps.h"
 #include "circt/Dialect/HW/HWOps.h"
+#include "circt/Support/CustomDirectiveImpl.h"
 #include "mlir/IR/Attributes.h"
 #include "mlir/IR/BuiltinTypes.h"
 #include "mlir/IR/Matchers.h"
@@ -24,6 +25,7 @@
 
 using namespace circt;
 using namespace mlir;
+using namespace llhd;
 
 unsigned circt::llhd::getLLHDTypeWidth(Type type) {
   if (auto sig = dyn_cast<hw::InOutType>(type))
@@ -64,6 +66,15 @@ void llhd::ConstantTimeOp::build(OpBuilder &builder, OperationState &result,
   return build(builder, result, TimeType::get(ctx), attr);
 }
 
+//===----------------------------------------------------------------------===//
+// SignalOp
+//===----------------------------------------------------------------------===//
+
+void SignalOp::getAsmResultNames(OpAsmSetValueNameFn setNameFn) {
+  if (getName() && !getName()->empty())
+    setNameFn(getResult(), *getName());
+}
+
 //===----------------------------------------------------------------------===//
 // SigExtractOp and PtrExtractOp
 //===----------------------------------------------------------------------===//

lib/Dialect/LLHD/Transforms/EarlyCodeMotionPass.cpp

@@ -70,7 +70,7 @@ void EarlyCodeMotionPass::runOnProcess(llhd::ProcessOp proc) {
     for (auto iter = block->getOperations().begin();
          iter != block->getOperations().end(); ++iter) {
       Operation &op = *iter;
-      if (!isa<llhd::PrbOp>(op) && !isa<llhd::SigOp>(op) &&
+      if (!isa<llhd::PrbOp>(op) && !isa<llhd::SignalOp>(op) &&
           (!mlir::isMemoryEffectFree(&op) ||
            op.hasTrait<OpTrait::IsTerminator>()))
         continue;

test/Conversion/MooreToCore/basic.mlir

@@ -369,31 +369,31 @@ moore.module @ParamTest(){
 
 moore.module @Variable() {
   // CHECK: [[TMP0:%.+]] = hw.constant 0 : i32
-  // CHECK: [[A:%.+]] = llhd.sig "a" [[TMP0]] : i32
+  // CHECK: %a = llhd.sig [[TMP0]] : i32
   %a = moore.variable : <i32>
 
   // CHECK: [[TMP1:%.+]] = hw.constant 0 : i8
-  // CHECK: [[B:%.+]] = llhd.sig "b1" [[TMP1]] : i8
+  // CHECK: %b1 = llhd.sig [[TMP1]] : i8
   %b1 = moore.variable : <i8>
 
-  // CHECK: [[PRB:%.+]] = llhd.prb [[B]] : !hw.inout<i8>
+  // CHECK: [[PRB:%.+]] = llhd.prb %b1 : !hw.inout<i8>
   %0 = moore.read %b1 : <i8>
-  // CHECK: llhd.sig "b2" [[PRB]] : i8
+  // CHECK: %b2 = llhd.sig [[PRB]] : i8
   %b2 = moore.variable %0 : <i8>
 
   // CHECK: %true = hw.constant true
   %1 = moore.constant 1 : l1
-  // CHECK: llhd.sig "l" %true : i1
+  // CHECK: %l = llhd.sig %true : i1
   %l = moore.variable %1 : <l1>
   // CHECK: [[TMP:%.+]] = hw.constant 0 : i19
-  // CHECK: llhd.sig "m" [[TMP]] : i19
+  // CHECK: %m = llhd.sig [[TMP]] : i19
   %m = moore.variable : <l19>
 
   // CHECK: [[TMP2:%.+]] = hw.constant 10 : i32
   %3 = moore.constant 10 : i32
 
   // CHECK: [[TIME:%.+]] = llhd.constant_time <0ns, 0d, 1e>
-  // CHECK: llhd.drv [[A]], [[TMP2]] after [[TIME]] : !hw.inout<i32>
+  // CHECK: llhd.drv %a, [[TMP2]] after [[TIME]] : !hw.inout<i32>
   moore.assign %a, %3 : i32
 
   // CHECK: hw.output
@@ -411,8 +411,8 @@ moore.module @Struct(in %a : !moore.i32, in %b : !moore.i32, in %arg0 : !moore.s
 
   // CHECK: [[C0:%.+]] = hw.constant 0 : i64
   // CHECK: [[INIT:%.+]] = hw.bitcast [[C0]] : (i64) -> !hw.struct<exp_bits: i32, man_bits: i32>
-  // CHECK: llhd.sig "" [[INIT]] : !hw.struct<exp_bits: i32, man_bits: i32>
-  // CHECK: llhd.sig "" %arg0 : !hw.struct<exp_bits: i32, man_bits: i32>
+  // CHECK: llhd.sig [[INIT]] : !hw.struct<exp_bits: i32, man_bits: i32>
+  // CHECK: llhd.sig %arg0 : !hw.struct<exp_bits: i32, man_bits: i32>
   %1 = moore.variable : <struct<{exp_bits: i32, man_bits: i32}>>
   %2 = moore.variable %arg0 : <struct<{exp_bits: i32, man_bits: i32}>>
 
@@ -427,10 +427,10 @@ moore.module @Struct(in %a : !moore.i32, in %b : !moore.i32, in %arg0 : !moore.s
 
 // CHECK-LABEL: hw.module @Process
 moore.module @Process(in %cond : i1) {
-  // CHECK: [[B:%.+]] = llhd.sig "b"
-  // CHECK: [[C:%.+]] = llhd.sig "c"
-  // CHECK: [[D:%.+]] = llhd.sig "d"
-  // CHECK: [[E:%.+]] = llhd.sig "e"
+  // CHECK: [[B:%b]] = llhd.sig
+  // CHECK: [[C:%c]] = llhd.sig
+  // CHECK: [[D:%d]] = llhd.sig
+  // CHECK: [[E:%e]] = llhd.sig
   %b = moore.variable : <i1>
   %c = moore.variable : <i1>
   %d = moore.variable : <i1>

test/Dialect/LLHD/IR/basic.mlir

@@ -90,22 +90,22 @@ func.func @check_store(%int : !llhd.ptr<i32>, %intC : i32 , %array : !llhd.ptr<!
 hw.module @checkSigInst() {
   // CHECK: %[[CI1:.*]] = hw.constant
   %cI1 = hw.constant 0 : i1
-  // CHECK-NEXT: %{{.*}} = llhd.sig "sigI1" %[[CI1]] : i1
-  %sigI1 = llhd.sig "sigI1" %cI1 : i1
+  // CHECK-NEXT: %sigI1 = llhd.sig %[[CI1]] : i1
+  %sigI1 = llhd.sig %cI1 : i1
   // CHECK-NEXT: %[[CI64:.*]] = hw.constant
   %cI64 = hw.constant 0 : i64
-  // CHECK-NEXT: %{{.*}} = llhd.sig "sigI64" %[[CI64]] : i64
-  %sigI64 = llhd.sig "sigI64" %cI64 : i64
+  // CHECK-NEXT: %sigI64 = llhd.sig %[[CI64]] : i64
+  %sigI64 = llhd.sig %cI64 : i64
 
   // CHECK-NEXT: %[[TUP:.*]] = hw.struct_create
   %tup = hw.struct_create (%cI1, %cI64) : !hw.struct<foo: i1, bar: i64>
-  // CHECK-NEXT: %{{.*}} = llhd.sig "sigTup" %[[TUP]] : !hw.struct<foo: i1, bar: i64>
-  %sigTup = llhd.sig "sigTup" %tup : !hw.struct<foo: i1, bar: i64>
+  // CHECK-NEXT: %sigTup = llhd.sig %[[TUP]] : !hw.struct<foo: i1, bar: i64>
+  %sigTup = llhd.sig %tup : !hw.struct<foo: i1, bar: i64>
 
   // CHECK-NEXT: %[[ARRAY:.*]] = hw.array_create
   %array = hw.array_create %cI1, %cI1 : i1
-  // CHECK-NEXT: %{{.*}} = llhd.sig "sigArray" %[[ARRAY]] : !hw.array<2xi1>
-  %sigArray = llhd.sig "sigArray" %array : !hw.array<2xi1>
+  // CHECK-NEXT: %sigArray = llhd.sig %[[ARRAY]] : !hw.array<2xi1>
+  %sigArray = llhd.sig %array : !hw.array<2xi1>
 }
 
 // CHECK-LABEL: @checkPrb