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[ExportVerilog] Make isVerilogExpression available to the Prepare pas…
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…s, NFC.
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lattner committed Aug 29, 2021
1 parent 5195616 commit 5cdf159
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Showing 2 changed files with 12 additions and 3 deletions.
9 changes: 6 additions & 3 deletions lib/Translation/ExportVerilog/ExportVerilog.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -72,7 +72,11 @@ static bool isDuplicatableNullaryExpression(Operation *op) {
return false;
}

static bool isVerilogExpression(Operation *op) {
/// This predicate returns true if the specified operation is considered a
/// potentially inlinable Verilog expression. These nodes always have a single
/// result, but may have side effects (e.g. `sv.verbatim.expr.se`).
/// MemoryEffects should be checked if a client cares.
bool ExportVerilog::isVerilogExpression(Operation *op) {
// These are SV dialect expressions.
if (isa<ReadInOutOp>(op) || isa<ArrayIndexInOutOp>(op))
return true;
Expand Down Expand Up @@ -1548,12 +1552,11 @@ void NameCollector::collectNames(Block &block) {
// Loop over all of the results of all of the ops. Anything that defines a
// value needs to be noticed.
for (auto &op : block) {
bool isExpr = isVerilogExpression(&op);

// Instances and interface instances are handled in prepareHWModule.
if (isa<InstanceOp, InterfaceInstanceOp>(op))
continue;

bool isExpr = isVerilogExpression(&op);
for (auto result : op.getResults()) {
// If this is an expression emitted inline or unused, it doesn't need a
// name.
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6 changes: 6 additions & 0 deletions lib/Translation/ExportVerilog/ExportVerilogInternals.h
Original file line number Diff line number Diff line change
Expand Up @@ -130,6 +130,12 @@ static inline bool isConstantExpression(Operation *op) {
return isa<hw::ConstantOp, sv::ConstantXOp, sv::ConstantZOp>(op);
}

/// This predicate returns true if the specified operation is considered a
/// potentially inlinable Verilog expression. These nodes always have a single
/// result, but may have side effects (e.g. `sv.verbatim.expr.se`).
/// MemoryEffects should be checked if a client cares.
bool isVerilogExpression(Operation *op);

/// For each module we emit, do a prepass over the structure, pre-lowering and
/// otherwise rewriting operations we don't want to emit.
void prepareHWModule(Block &block, ModuleNameManager &names,
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