[Arc][NFC] Tweak arc op docs and add missing test

Slightly tweak the summary and description fields of a few Arc ops and add missing tests for `arc.state_write` and `arc.state_read` to the basic Arc dialect test.
llvm · Oct 14, 2024 · 822ac6b · 822ac6b
1 parent 3e3345e
commit 822ac6b
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Showing 2 changed files with 26 additions and 37 deletions.
diff --git a/include/circt/Dialect/Arc/ArcOps.td b/include/circt/Dialect/Arc/ArcOps.td
@@ -375,13 +375,12 @@ def MemoryReadOp : ArcOp<"memory_read", [
   MemoryAndDataTypesMatch<"memory", "data">,
   MemoryAndAddressTypesMatch<"memory", "address">
 ]> {
-  let summary = "Read word from memory";
+  let summary = "Read a word from a memory";
   let arguments = (ins
     MemoryType:$memory,
     AnyInteger:$address
   );
   let results = (outs AnyInteger:$data);
-
   let assemblyFormat = [{
     $memory `[` $address `]` attr-dict `:` type($memory)
   }];
@@ -392,19 +391,17 @@ def MemoryWriteOp : ArcOp<"memory_write", [
   MemoryAndDataTypesMatch<"memory", "data">,
   MemoryAndAddressTypesMatch<"memory", "address">
 ]> {
-  let summary = "Write word to memory";
+  let summary = "Write a word to a memory";
   let arguments = (ins
     MemoryType:$memory,
     AnyInteger:$address,
     Optional<I1>:$enable,
     AnyInteger:$data
   );
-
   let assemblyFormat = [{
     $memory `[` $address `]` `,` $data (`if` $enable^)?
     attr-dict `:` type($memory)
   }];
-
   let hasFolder = 1;
   let hasCanonicalizeMethod = 1;
 }
@@ -555,9 +552,9 @@ class StateAndValueTypesMatch<string state, string value> : TypesMatchWith<
 
 def StateReadOp : ArcOp<"state_read", [
   MemoryEffects<[MemRead]>,
-  StateAndValueTypesMatch<"state", "value">
+  StateAndValueTypesMatch<"state", "value">,
 ]> {
-  let summary = "Get a state's current value";
+  let summary = "Read a state's value";
   let arguments = (ins StateType:$state);
   let results = (outs AnyType:$value);
   let assemblyFormat = [{
@@ -567,24 +564,14 @@ def StateReadOp : ArcOp<"state_read", [
 
 def StateWriteOp : ArcOp<"state_write", [
   MemoryEffects<[MemWrite]>,
-  StateAndValueTypesMatch<"state", "value">
+  StateAndValueTypesMatch<"state", "value">,
 ]> {
   let summary = "Update a state's value";
-  let description = [{
-    Changes the value of a state. This operation is treated as a deferred
-    assignment by most transformation passes, which allows them to change the
-    order of `arc.state_read` and `arc.state_write` ops on the same state
-    without affecting the correctness of the model. The reads are always assumed
-    to produce the current value of the state and writes to be deferred until
-    all operations in the model have been executed for the current time step.
-
-    The only exceptions to this are the state update legalization pass, which
-    inserts the necessary temporary variables such that writes can be performed
-    immediately without affecting correctness. This allows later lowering passes
-    to treat `arc.state_write` as an immediate assignment (without defering).
-  }];
-  let arguments = (ins StateType:$state, AnyType:$value,
-                       Optional<I1>:$condition);
+  let arguments = (ins
+    StateType:$state,
+    AnyType:$value,
+    Optional<I1>:$condition
+  );
   let assemblyFormat = [{
     $state `=` $value (`if` $condition^)? attr-dict `:` type($state)
   }];
@@ -670,7 +657,7 @@ def SimEmitValueOp : ArcOp<"sim.emit"> {
 
 def TapOp : ArcOp<"tap"> {
   let summary = "A tracker op to observe a value under a given name";
-  let arguments = (ins AnySignlessInteger:$value, StrAttr:$name);
+  let arguments = (ins AnyType:$value, StrAttr:$name);
   let assemblyFormat = [{ $value attr-dict `:` type($value) }];
 }
 

diff --git a/test/Dialect/Arc/basic.mlir b/test/Dialect/Arc/basic.mlir
@@ -1,4 +1,4 @@
-// RUN: circt-opt %s --verify-diagnostics -split-input-file | circt-opt | FileCheck %s
+// RUN: circt-opt %s --verify-diagnostics | circt-opt | FileCheck %s
 
 // CHECK-LABEL: arc.define @Foo
 arc.define @Foo(%arg0: i42, %arg1: i9) -> (i42, i9) {
@@ -159,8 +159,6 @@ arc.define @identity3(%arg0: i32, %arg1: i32, %arg2: i32) -> (i32, i32, i32) {
   arc.output %arg0, %arg1, %arg2 : i32, i32, i32
 }
 
-// -----
-
 hw.module @vectorize_in_clock_domain(in %in0: i2, in %in1: i2, in %in2: i1, in %in3: i1, in %clk: !seq.clock, out out0: i1, out out1: i1) {
   %0:2 = arc.clock_domain (%in0, %in1, %in2, %in3) clock %clk : (i2, i2, i1, i1) -> (i1, i1) {
     ^bb0(%arg0: i2, %arg1: i2, %arg2: i1, %arg3: i1):
@@ -187,8 +185,6 @@ arc.define @vectorizable(%arg0: i2, %arg1: i1) -> i1 {
 //       CHECK:   arc.vectorize.return [[V1]] : i1
 //       CHECK: }
 
-// -----
-
 hw.module @vectorize(in %in0: i1, in %in1: i1, in %in2: i1, in %in3: i1, out out0: i1, out out1: i1, out out2: i1) {
   %0:2 = arc.vectorize (%in0, %in1), (%in2, %in3) : (i1, i1, i1, i1) -> (i1, i1) {
   ^bb0(%arg0: i1, %arg1: i1):
@@ -216,8 +212,6 @@ hw.module @vectorize(in %in0: i1, in %in1: i1, in %in2: i1, in %in3: i1, out out
 //       CHECK: }
 //       CHECK: hw.output [[V0]]#0, [[V0]]#1, [[V2]] :
 
-// -----
-
 hw.module @vectorize_body_lowered(in %in0: i1, in %in1: i1, in %in2: i1, in %in3: i1, out out0: i1, out out1: i1, out out2: i1, out out3: i1) {
   %0:2 = arc.vectorize (%in0, %in1), (%in2, %in2) : (i1, i1, i1, i1) -> (i1, i1) {
   ^bb0(%arg0: i2, %arg1: i2):
@@ -248,8 +242,6 @@ hw.module @vectorize_body_lowered(in %in0: i1, in %in1: i1, in %in2: i1, in %in3
 //       CHECK: }
 //       CHECK: hw.output [[V0]]#0, [[V0]]#1, [[V2]]#0, [[V2]]#1 :
 
-// -----
-
 hw.module @vectorize_boundary_lowered(in %in0: i1, in %in1: i1, in %in2: i1, in %in3: i1, out out0: i1, out out1: i1, out out2: i1, out out3: i1) {
   %0 = comb.concat %in0, %in1 : i1, i1
   %1 = comb.replicate %in2 : (i1) -> i2
@@ -298,8 +290,6 @@ hw.module @vectorize_boundary_lowered(in %in0: i1, in %in1: i1, in %in2: i1, in
 //       CHECK: [[V9:%.+]] = vector.extract [[V7]][1]
 //       CHECK: hw.output [[V3]], [[V4]], [[V8]], [[V9]] :
 
-// -----
-
 hw.module @vectorize_both_sides_lowered(in %in0: i1, in %in1: i1, in %in2: i1, in %in3: i1, out out0: i1, out out1: i1, out out2: i1, out out3: i1) {
   %0 = comb.concat %in0, %in1 : i1, i1
   %1 = comb.replicate %in2 : (i1) -> i2
@@ -348,8 +338,6 @@ hw.module @vectorize_both_sides_lowered(in %in0: i1, in %in1: i1, in %in2: i1, i
 //       CHECK: [[V9:%.+]] = vector.extract [[V7]][1]
 //       CHECK: hw.output [[V3]], [[V4]], [[V8]], [[V9]] :
 
-// -----
-
 // CHECK-LABEL: hw.module @sim_test
 hw.module @sim_test(in %a : i8, out b : i8) {
   hw.output %a : i8
@@ -368,3 +356,17 @@ func.func @with_attr() {
   arc.sim.instantiate @sim_test as %model attributes {foo = "foo"} {}
   return
 }
+
+// CHECK-LABEL: func.func @ReadsWrites(
+// CHECK-SAME: %arg0: !arc.state<i42>
+// CHECK-SAME: %arg1: i42
+// CHECK-SAME: %arg2: i1
+func.func @ReadsWrites(%arg0: !arc.state<i42>, %arg1: i42, %arg2: i1) {
+  // CHECK: arc.state_read %arg0 : <i42>
+  arc.state_read %arg0 : <i42>
+  // CHECK: arc.state_write %arg0 = %arg1 : <i42>
+  arc.state_write %arg0 = %arg1 : <i42>
+  // CHECK: arc.state_write %arg0 = %arg1 if %arg2 : <i42>
+  arc.state_write %arg0 = %arg1 if %arg2 : <i42>
+  return
+}