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[LLHD][NFC] Clean up regression tests a bit #7507

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Aug 11, 2024
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[LLHD][NFC] Clean up regression tests a bit #7507

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212 changes: 212 additions & 0 deletions test/Dialect/LLHD/IR/basic.mlir
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Expand Up @@ -7,3 +7,215 @@ hw.module @basic(in %in0 : i32, out out0 : i32) {
%0 = llhd.delay %in0 by <0ns, 1d, 0e> : i32
hw.output %0 : i32
}

// CHECK-LABEL: @connect_ports
// CHECK-SAME: (inout %[[IN:.+]] : [[TYPE:.+]], inout %[[OUT:.+]] : [[TYPE]])
// CHECK-NEXT: llhd.con %[[IN]], %[[OUT]] : !hw.inout<[[TYPE]]>
hw.module @connect_ports(inout %in: i32, inout %out: i32) {
llhd.con %in, %out : !hw.inout<i32>
}

// CHECK-LABEL: @sigExtract
hw.module @sigExtract(inout %arg0 : i32, in %arg1 : i5) {
// CHECK-NEXT: %{{.*}} = llhd.sig.extract %arg0 from %arg1 : (!hw.inout<i32>) -> !hw.inout<i5>
%1 = llhd.sig.extract %arg0 from %arg1 : (!hw.inout<i32>) -> !hw.inout<i5>
}

// CHECK-LABEL: @sigArray
hw.module @sigArray(inout %arg0 : !hw.array<5xi1>, in %arg1 : i3) {
// CHECK-NEXT: %{{.*}} = llhd.sig.array_slice %arg0 at %arg1 : (!hw.inout<array<5xi1>>) -> !hw.inout<array<3xi1>>
%0 = llhd.sig.array_slice %arg0 at %arg1 : (!hw.inout<array<5xi1>>) -> !hw.inout<array<3xi1>>
// CHECK-NEXT: %{{.*}} = llhd.sig.array_get %arg0[%arg1] : !hw.inout<array<5xi1>>
%1 = llhd.sig.array_get %arg0[%arg1] : !hw.inout<array<5xi1>>
}

// CHECK-LABEL: @sigStructExtract
hw.module @sigStructExtract(inout %arg0 : !hw.struct<foo: i1, bar: i2, baz: i3>) {
// CHECK-NEXT: %{{.*}} = llhd.sig.struct_extract %arg0["foo"] : !hw.inout<struct<foo: i1, bar: i2, baz: i3>>
%0 = llhd.sig.struct_extract %arg0["foo"] : !hw.inout<struct<foo: i1, bar: i2, baz: i3>>
// CHECK-NEXT: %{{.*}} = llhd.sig.struct_extract %arg0["baz"] : !hw.inout<struct<foo: i1, bar: i2, baz: i3>>
%1 = llhd.sig.struct_extract %arg0["baz"] : !hw.inout<struct<foo: i1, bar: i2, baz: i3>>
}

// CHECK-LABEL: @check_var
// CHECK-SAME: %[[INT:.*]]: i32
// CHECK-SAME: %[[ARRAY:.*]]: !hw.array<3xi1>
// CHECK-SAME: %[[TUP:.*]]: !hw.struct<foo: i1, bar: i2, baz: i3>
func.func @check_var(%int : i32, %array : !hw.array<3xi1>, %tup : !hw.struct<foo: i1, bar: i2, baz: i3>) {
// CHECK-NEXT: %{{.*}} = llhd.var %[[INT]] : i32
%0 = llhd.var %int : i32
// CHECK-NEXT: %{{.*}} = llhd.var %[[ARRAY]] : !hw.array<3xi1>
%1 = llhd.var %array : !hw.array<3xi1>
// CHECK-NEXT: %{{.*}} = llhd.var %[[TUP]] : !hw.struct<foo: i1, bar: i2, baz: i3>
%2 = llhd.var %tup : !hw.struct<foo: i1, bar: i2, baz: i3>

return
}

// CHECK-LABEL: @check_load
// CHECK-SAME: %[[INT:.*]]: !llhd.ptr<i32>
// CHECK-SAME: %[[ARRAY:.*]]: !llhd.ptr<!hw.array<3xi1>>
// CHECK-SAME: %[[TUP:.*]]: !llhd.ptr<!hw.struct<foo: i1, bar: i2, baz: i3>>
func.func @check_load(%int : !llhd.ptr<i32>, %array : !llhd.ptr<!hw.array<3xi1>>, %tup : !llhd.ptr<!hw.struct<foo: i1, bar: i2, baz: i3>>) {
// CHECK-NEXT: %{{.*}} = llhd.load %[[INT]] : !llhd.ptr<i32>
%0 = llhd.load %int : !llhd.ptr<i32>
// CHECK-NEXT: %{{.*}} = llhd.load %[[ARRAY]] : !llhd.ptr<!hw.array<3xi1>>
%1 = llhd.load %array : !llhd.ptr<!hw.array<3xi1>>
// CHECK-NEXT: %{{.*}} = llhd.load %[[TUP]] : !llhd.ptr<!hw.struct<foo: i1, bar: i2, baz: i3>>
%2 = llhd.load %tup : !llhd.ptr<!hw.struct<foo: i1, bar: i2, baz: i3>>

return

}

// CHECK-LABEL: @check_store
// CHECK-SAME: %[[INT:.*]]: !llhd.ptr<i32>
// CHECK-SAME: %[[INTC:.*]]: i32
// CHECK-SAME: %[[ARRAY:.*]]: !llhd.ptr<!hw.array<3xi1>>
// CHECK-SAME: %[[ARRAYC:.*]]: !hw.array<3xi1>
// CHECK-SAME: %[[TUP:.*]]: !llhd.ptr<!hw.struct<foo: i1, bar: i2, baz: i3>>
// CHECK-SAME: %[[TUPC:.*]]: !hw.struct<foo: i1, bar: i2, baz: i3>
func.func @check_store(%int : !llhd.ptr<i32>, %intC : i32 , %array : !llhd.ptr<!hw.array<3xi1>>, %arrayC : !hw.array<3xi1>, %tup : !llhd.ptr<!hw.struct<foo: i1, bar: i2, baz: i3>>, %tupC : !hw.struct<foo: i1, bar: i2, baz: i3>) {
// CHECK-NEXT: llhd.store %[[INT]], %[[INTC]] : !llhd.ptr<i32>
llhd.store %int, %intC : !llhd.ptr<i32>
// CHECK-NEXT: llhd.store %[[ARRAY]], %[[ARRAYC]] : !llhd.ptr<!hw.array<3xi1>>
llhd.store %array, %arrayC : !llhd.ptr<!hw.array<3xi1>>
// CHECK-NEXT: llhd.store %[[TUP]], %[[TUPC]] : !llhd.ptr<!hw.struct<foo: i1, bar: i2, baz: i3>>
llhd.store %tup, %tupC : !llhd.ptr<!hw.struct<foo: i1, bar: i2, baz: i3>>

return
}

// CHECK-LABEL: @checkSigInst
hw.module @checkSigInst() {
// CHECK: %[[CI1:.*]] = hw.constant
%cI1 = hw.constant 0 : i1
// CHECK-NEXT: %{{.*}} = llhd.sig "sigI1" %[[CI1]] : i1
%sigI1 = llhd.sig "sigI1" %cI1 : i1
// CHECK-NEXT: %[[CI64:.*]] = hw.constant
%cI64 = hw.constant 0 : i64
// CHECK-NEXT: %{{.*}} = llhd.sig "sigI64" %[[CI64]] : i64
%sigI64 = llhd.sig "sigI64" %cI64 : i64

// CHECK-NEXT: %[[TUP:.*]] = hw.struct_create
%tup = hw.struct_create (%cI1, %cI64) : !hw.struct<foo: i1, bar: i64>
// CHECK-NEXT: %{{.*}} = llhd.sig "sigTup" %[[TUP]] : !hw.struct<foo: i1, bar: i64>
%sigTup = llhd.sig "sigTup" %tup : !hw.struct<foo: i1, bar: i64>

// CHECK-NEXT: %[[ARRAY:.*]] = hw.array_create
%array = hw.array_create %cI1, %cI1 : i1
// CHECK-NEXT: %{{.*}} = llhd.sig "sigArray" %[[ARRAY]] : !hw.array<2xi1>
%sigArray = llhd.sig "sigArray" %array : !hw.array<2xi1>
}

// CHECK-LABEL: @checkPrb
hw.module @checkPrb(inout %arg0 : i1, inout %arg1 : i64, inout %arg2 : !hw.array<3xi8>, inout %arg3 : !hw.struct<foo: i1, bar: i2, baz: i4>) {
// CHECK: %{{.*}} = llhd.prb %arg0 : !hw.inout<i1>
%0 = llhd.prb %arg0 : !hw.inout<i1>
// CHECK-NEXT: %{{.*}} = llhd.prb %arg1 : !hw.inout<i64>
%1 = llhd.prb %arg1 : !hw.inout<i64>
// CHECK-NEXT: %{{.*}} = llhd.prb %arg2 : !hw.inout<array<3xi8>>
%2 = llhd.prb %arg2 : !hw.inout<array<3xi8>>
// CHECK-NEXT: %{{.*}} = llhd.prb %arg3 : !hw.inout<struct<foo: i1, bar: i2, baz: i4>>
%3 = llhd.prb %arg3 : !hw.inout<struct<foo: i1, bar: i2, baz: i4>>
}

// CHECK-LABEL: @checkOutput
hw.module @checkOutput(in %arg0 : i32) {
%t = llhd.constant_time <0ns, 1d, 0e>
// CHECK: %{{.+}} = llhd.output %arg0 after %{{.*}} : i32
%0 = llhd.output %arg0 after %t : i32
// CHECK-NEXT: %{{.+}} = llhd.output "sigName" %arg0 after %{{.*}} : i32
%1 = llhd.output "sigName" %arg0 after %t : i32
}

// CHECK-LABEL: @checkDrv
hw.module @checkDrv(inout %arg0 : i1, inout %arg1 : i64, in %arg2 : i1,
in %arg3 : i64, inout %arg5 : !hw.array<3xi8>,
inout %arg6 : !hw.struct<foo: i1, bar: i2, baz: i4>,
in %arg7 : !hw.array<3xi8>, in %arg8 : !hw.struct<foo: i1, bar: i2, baz: i4>) {

%t = llhd.constant_time <0ns, 1d, 0e>
// CHECK: llhd.drv %arg0, %arg2 after %{{.*}} : !hw.inout<i1>
llhd.drv %arg0, %arg2 after %t : !hw.inout<i1>
// CHECK-NEXT: llhd.drv %arg1, %arg3 after %{{.*}} : !hw.inout<i64>
llhd.drv %arg1, %arg3 after %t : !hw.inout<i64>
// CHECK-NEXT: llhd.drv %arg1, %arg3 after %{{.*}} if %arg2 : !hw.inout<i64>
llhd.drv %arg1, %arg3 after %t if %arg2 : !hw.inout<i64>
// CHECK-NEXT: llhd.drv %arg5, %arg7 after %{{.*}} : !hw.inout<array<3xi8>>
llhd.drv %arg5, %arg7 after %t : !hw.inout<array<3xi8>>
// CHECK-NEXT: llhd.drv %arg6, %arg8 after %{{.*}} : !hw.inout<struct<foo: i1, bar: i2, baz: i4>>
llhd.drv %arg6, %arg8 after %t : !hw.inout<struct<foo: i1, bar: i2, baz: i4>>
}

// CHECK-LABEL: @check_wait_0
hw.module @check_wait_0 () {
// CHECK-NEXT: llhd.process
llhd.process {
// CHECK: llhd.wait ^[[BB:.*]]
llhd.wait ^bb1
// CHECK-NEXT: ^[[BB]]
^bb1:
llhd.halt
}
}

// CHECK-LABEL: @check_wait_1
hw.module @check_wait_1 () {
// CHECK-NEXT: llhd.process
llhd.process {
// CHECK-NEXT: %[[TIME:.*]] = llhd.constant_time
%time = llhd.constant_time #llhd.time<0ns, 0d, 0e>
// CHECK-NEXT: llhd.wait for %[[TIME]], ^[[BB:.*]](%[[TIME]] : !llhd.time)
llhd.wait for %time, ^bb1(%time: !llhd.time)
// CHECK-NEXT: ^[[BB]](%[[T:.*]]: !llhd.time):
^bb1(%t: !llhd.time):
llhd.halt
}
}

// CHECK: @check_wait_2(inout %[[ARG0:.*]] : i64, inout %[[ARG1:.*]] : i1) {
hw.module @check_wait_2 (inout %arg0 : i64, inout %arg1 : i1) {
// CHECK-NEXT: llhd.process
llhd.process {
// CHECK-NEXT: llhd.wait (%[[ARG0]], %[[ARG1]] : !hw.inout<i64>, !hw.inout<i1>), ^[[BB:.*]](%[[ARG1]] : !hw.inout<i1>)
llhd.wait (%arg0, %arg1 : !hw.inout<i64>, !hw.inout<i1>), ^bb1(%arg1 : !hw.inout<i1>)
// CHECK: ^[[BB]](%[[A:.*]]: !hw.inout<i1>):
^bb1(%a: !hw.inout<i1>):
llhd.halt
}
}

// CHECK: hw.module @check_wait_3(inout %[[ARG0:.*]] : i64, inout %[[ARG1:.*]] : i1) {
hw.module @check_wait_3 (inout %arg0 : i64, inout %arg1 : i1) {
// CHECK-NEXT: llhd.process
llhd.process {
// CHECK-NEXT: %[[TIME:.*]] = llhd.constant_time
%time = llhd.constant_time #llhd.time<0ns, 0d, 0e>
// CHECK-NEXT: llhd.wait for %[[TIME]], (%[[ARG0]], %[[ARG1]] : !hw.inout<i64>, !hw.inout<i1>), ^[[BB:.*]](%[[ARG1]], %[[ARG0]] : !hw.inout<i1>, !hw.inout<i64>)
llhd.wait for %time, (%arg0, %arg1 : !hw.inout<i64>, !hw.inout<i1>), ^bb1(%arg1, %arg0 : !hw.inout<i1>, !hw.inout<i64>)
// CHECK: ^[[BB]](%[[A:.*]]: !hw.inout<i1>, %[[B:.*]]: !hw.inout<i64>):
^bb1(%a: !hw.inout<i1>, %b: !hw.inout<i64>):
llhd.halt
}
}

// CHECK-LABEL: @check_reg
// CHECK-SAME: %[[IN64:.*]] : i64
hw.module @check_reg(inout %in64 : i64) {
// CHECK: %[[C1:.*]] = hw.constant
%c1 = hw.constant 0 : i1
// CHECK-NEXT: %[[C64:.*]] = hw.constant
%c64 = hw.constant 0 : i64
// CHECK-NEXT: %[[TIME:.*]] = llhd.constant_time
%time = llhd.constant_time #llhd.time<1ns, 0d, 0e>
// one trigger with optional gate
// CHECK-NEXT: llhd.reg %[[IN64]], (%[[C64]], "low" %[[C1]] after %[[TIME]] if %[[C1]] : i64) : !hw.inout<i64>
"llhd.reg"(%in64, %c64, %c1, %time, %c1) {modes=[0], gateMask=[1], operandSegmentSizes=array<i32: 1,1,1,1,1>} : (!hw.inout<i64>, i64, i1, !llhd.time, i1) -> ()
// two triggers with optional gates
// CHECK-NEXT: llhd.reg %[[IN64]], (%[[C64]], "low" %[[C1]] after %[[TIME]] if %[[C1]] : i64), (%[[IN64]], "high" %[[C1]] after %[[TIME]] if %[[C1]] : !hw.inout<i64>) : !hw.inout<i64>
"llhd.reg"(%in64, %c64, %in64, %c1, %c1, %time, %time, %c1, %c1) {modes=[0,1], gateMask=[1,2], operandSegmentSizes=array<i32: 1,2,2,2,2>} : (!hw.inout<i64>, i64, !hw.inout<i64>, i1, i1, !llhd.time, !llhd.time, i1, i1) -> ()
// two triggers with only one optional gate
// CHECK-NEXT: llhd.reg %[[IN64]], (%[[C64]], "low" %[[C1]] after %[[TIME]] : i64), (%[[IN64]], "high" %[[C1]] after %[[TIME]] if %[[C1]] : !hw.inout<i64>) : !hw.inout<i64>
"llhd.reg"(%in64, %c64, %in64, %c1, %c1, %time, %time, %c1) {modes=[0,1], gateMask=[0,1], operandSegmentSizes=array<i32: 1,2,2,2,1>} : (!hw.inout<i64>, i64, !hw.inout<i64>, i1, i1, !llhd.time, !llhd.time, i1) -> ()
}
16 changes: 0 additions & 16 deletions test/Dialect/LLHD/IR/connect-errors.mlir
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8 changes: 0 additions & 8 deletions test/Dialect/LLHD/IR/connect.mlir
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117 changes: 117 additions & 0 deletions test/Dialect/LLHD/IR/errors.mlir
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Expand Up @@ -5,3 +5,120 @@ hw.module @errors(in %in0: i32, out out0: i8) {
%0 = "llhd.delay"(%in0) {delay = #llhd.time<0ns, 1d, 0e>} : (i32) -> i8
hw.output %0 : i8
}

// -----

// expected-note @+1 {{prior use here}}
hw.module @connect_different_types(inout %in: i8, inout %out: i32) {
// expected-error @+1 {{use of value '%out' expects different type}}
llhd.con %in, %out : !hw.inout<i8>
}

// -----

hw.module @connect_non_signals(inout %in: i32, inout %out: i32) {
%0 = llhd.prb %in : !hw.inout<i32>
%1 = llhd.prb %out : !hw.inout<i32>
// expected-error @+1 {{'llhd.con' op operand #0 must be InOutType, but got 'i32'}}
llhd.con %0, %1 : i32
}

// -----

hw.module @illegal_signal_to_array(inout %sig : !hw.array<3xi32>, in %ind : i2) {
// expected-error @+1 {{'llhd.sig.array_slice' op result #0 must be InOutType of an ArrayType values, but got '!hw.array<3xi32>'}}
%0 = llhd.sig.array_slice %sig at %ind : (!hw.inout<array<3xi32>>) -> !hw.array<3xi32>
}

// -----

hw.module @illegal_array_element_type_mismatch(inout %sig : !hw.array<3xi32>, in %ind : i2) {
// expected-error @+1 {{arrays element type must match}}
%0 = llhd.sig.array_slice %sig at %ind : (!hw.inout<array<3xi32>>) -> !hw.inout<array<2xi1>>
}

// -----

hw.module @illegal_result_array_too_big(inout %sig : !hw.array<3xi32>, in %ind : i2) {
// expected-error @+1 {{width of result type has to be smaller than or equal to the input type}}
%0 = llhd.sig.array_slice %sig at %ind : (!hw.inout<array<3xi32>>) -> !hw.inout<array<4xi32>>
}

// -----

hw.module @illegal_sig_to_int(inout %s : i32, in %ind : i5) {
// expected-error @+1 {{'llhd.sig.extract' op result #0 must be InOutType of a signless integer bitvector values, but got 'i10'}}
%0 = llhd.sig.extract %s from %ind : (!hw.inout<i32>) -> i10
}

// -----

hw.module @illegal_sig_to_int_to_wide(inout %s : i32, in %ind : i5) {
// expected-error @+1 {{width of result type has to be smaller than or equal to the input type}}
%0 = llhd.sig.extract %s from %ind : (!hw.inout<i32>) -> !hw.inout<i64>
}

// -----

hw.module @extract_element_tuple_index_out_of_bounds(inout %tup : !hw.struct<foo: i1, bar: i2, baz: i3>) {
// expected-error @+1 {{invalid field name specified}}
%0 = llhd.sig.struct_extract %tup["foobar"] : !hw.inout<struct<foo: i1, bar: i2, baz: i3>>
}

// -----

// expected-note @+1 {{prior use here}}
func.func @check_illegal_store(%i1Ptr : !llhd.ptr<i1>, %i32Const : i32) {
// expected-error @+1 {{use of value '%i32Const' expects different type than prior uses: 'i1' vs 'i32'}}
llhd.store %i1Ptr, %i32Const : !llhd.ptr<i1>

return
}

// -----

// expected-error @+1 {{unknown type `illegaltype` in dialect `llhd`}}
func.func @illegaltype(%arg0: !llhd.illegaltype) {
return
}

// -----

// expected-error @+2 {{unknown attribute `illegalattr` in dialect `llhd`}}
func.func @illegalattr() {
%0 = llhd.constant_time #llhd.illegalattr : i1
return
}

// -----

// expected-error @+3 {{failed to verify that type of 'init' and underlying type of 'signal' have to match.}}
hw.module @check_illegal_sig() {
%cI1 = hw.constant 0 : i1
%sig1 = "llhd.sig"(%cI1) {name="foo"} : (i1) -> !hw.inout<i32>
}

// -----

// expected-error @+2 {{failed to verify that type of 'result' and underlying type of 'signal' have to match.}}
hw.module @check_illegal_prb(inout %sig : i1) {
%prb = "llhd.prb"(%sig) {} : (!hw.inout<i1>) -> i32
}

// -----

// expected-error @+4 {{failed to verify that type of 'value' and underlying type of 'signal' have to match.}}
hw.module @check_illegal_drv(inout %sig : i1) {
%c = hw.constant 0 : i32
%time = llhd.constant_time #llhd.time<1ns, 0d, 0e>
"llhd.drv"(%sig, %c, %time) {} : (!hw.inout<i1>, i32, !llhd.time) -> ()
}

// -----

func.func @illegal_sig_parent(%arg0 : i1) {
// expected-error @+1 {{expects parent op to be one of 'hw.module, llhd.process'}}
%0 = llhd.sig "sig" %arg0 : i1

return
}
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