[MooreToCore] Add support for format strings and display task #7694
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fabianschuiki
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fzi-hielscher,
maerhart and
hailongSun2000
Lower the format string ops and the `moore.builtin.display` task to the corresponding ops in the Sim dialect. This is not perfect yet, since Sim does not support some of the formatting options. They will be easy to add in the future though.
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| // TODO: These should honor the width, alignment, and padding. | ||
| switch (op.getFormat()) { | ||
| case IntFormat::Decimal: | ||
| rewriter.replaceOpWithNewOp<sim::FormatDecOp>(op, adaptor.getValue()); |
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Do we have a way of handling signedness here? By not setting the signed attribute the value will always get formatted as unsigned. How would we deal with the difference in this example:
module tb;
byte foo = 8'h80;
initial $display("Signed: %d", $signed(foo));
initial $display("Unsigned: %d", $unsigned(foo));
endmoduleThere was a problem hiding this comment.
That's a great point. Do you know what the standard says how your example would be printed? Does %d check the type's signedness?
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I don't see any mention of the sign in the LRM. But for once all simulators on edaplayground agree: It depends on the type's signedness. The above example is the same as
module tb;
logic signed [7:0] fooS = 8'h80;
logic [7:0] fooU = 8'h80;
initial $display("Signed: %d", fooS); // "Signed: -128"
initial $display("Unsigned: %d", fooU); // "Unsigned: 128"
endmoduleI wish they'd also agree on the padding...
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🎉 Nice! I also love how the %d field expands to the maximum width a decimal number can have, 3, but then adds a random - in front that throws everything off 🤣. I love how SV consistently picks the wrong default for a lot of things.
Lower the format string ops and the
moore.builtin.displaytask to the corresponding ops in the Sim dialect. This is not perfect yet, since Sim does not support some of the formatting options. They will be easy to add in the future though.