[arcilator] Add clock divider integration test #7705
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There was a problem hiding this comment.
This needs #7703 to work correctly, doesn't it?
Independently of that, it is currently blasting through the C calling conventions, giving me this output locally:
0 0 2191024128 1808528296
0 0 2191024128 1808528296
0 0 2191024128 1808528296
[...]
The changes below should fix that.
|
Uh oh, damn calling conventions 🙈. Thanks for the fixes @fzi-hielscher 🥳. |
uenoku
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Oct 15, 2024
maerhart
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Oct 15, 2024
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Add a test to check that arcilator can simulate a simple clock divider. This exercises a corner case of arcilator's simulation model scheduling, where a state updating its value can trigger other states and module outptus to update their values. In this case, a cascade of clock edges is generated by feeding one state's output into the clock input of the next state.
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Add a test to check that arcilator can simulate a simple clock divider. This exercises a corner case of arcilator's simulation model scheduling, where a state updating its value can trigger other states and module outptus to update their values. In this case, a cascade of clock edges is generated by feeding one state's output into the clock input of the next state.