[FIRRTL] Add View Intrinsic

include/circt/Dialect/FIRRTL/FIRRTLIntrinsics.td

@@ -231,4 +231,16 @@ def DPICallIntrinsicOp : FIRRTLOp<"int.dpi.call",
   let hasVerifier = 1;
 }
 
+def ViewIntrinsicOp : FIRRTLOp<"view", []> {
+  let summary = "A SystemVerilog Interface only usable for waveform debugging";
+  let description = [{
+    This will become a SystemVerilog Interface that is driven by its arguments.
+    This is _not_ intended to be used for anything other than assistance when
+    debugging in a waveform.  This is _not_ a true SystemVerilog Interface, it
+    is only lowered to one.
+  }];
+  let arguments = (ins StrAttr:$name, AugmentedBundleType:$augmentedType, Variadic<GroundType>:$inputs);
+  let assemblyFormat = "$name `,` $augmentedType (`,` $inputs^)? attr-dict (`:` type($inputs)^)?";
+}
+
 #endif // CIRCT_DIALECT_FIRRTL_FIRRTLINTRINSICS_TD

include/circt/Dialect/FIRRTL/FIRRTLTypes.td

@@ -81,6 +81,10 @@ def AggregateType : FIRRTLDialectType<
   CPred<"type_isa<FVectorType, BundleType, FEnumType>($_self)">,
   "a aggregate type", "::circt::firrtl::FIRRTLBaseType">;
 
+def GroundType : FIRRTLDialectType<
+  CPred<"llvm::isa<FIRRTLBaseType>($_self) && cast<FIRRTLBaseType>($_self).isGround()">,
+  "a ground type", "::circt::firrtl::FIRRTLBaseType">;
+
 def PassiveType : FIRRTLDialectType<
   CPred<"type_isa<FIRRTLBaseType>($_self) && cast<FIRRTLBaseType>($_self).isPassive()">,
   "a passive base type (contain no flips)", "::circt::firrtl::FIRRTLBaseType">;

include/circt/Dialect/FIRRTL/FIRRTLVisitors.h

@@ -236,13 +236,13 @@ class StmtVisitor {
   ResultType dispatchStmtVisitor(Operation *op, ExtraArgs... args) {
     auto *thisCast = static_cast<ConcreteType *>(this);
     return TypeSwitch<Operation *, ResultType>(op)
-        .template Case<AttachOp, ConnectOp, MatchingConnectOp, RefDefineOp,
-                       ForceOp, PrintFOp, SkipOp, StopOp, WhenOp, AssertOp,
-                       AssumeOp, CoverOp, PropAssignOp, RefForceOp,
-                       RefForceInitialOp, RefReleaseOp, RefReleaseInitialOp,
-                       FPGAProbeIntrinsicOp, VerifAssertIntrinsicOp,
-                       VerifAssumeIntrinsicOp, UnclockedAssumeIntrinsicOp,
-                       VerifCoverIntrinsicOp, LayerBlockOp, MatchOp>(
+        .template Case<
+            AttachOp, ConnectOp, MatchingConnectOp, RefDefineOp, ForceOp,
+            PrintFOp, SkipOp, StopOp, WhenOp, AssertOp, AssumeOp, CoverOp,
+            PropAssignOp, RefForceOp, RefForceInitialOp, RefReleaseOp,
+            RefReleaseInitialOp, FPGAProbeIntrinsicOp, VerifAssertIntrinsicOp,
+            VerifAssumeIntrinsicOp, UnclockedAssumeIntrinsicOp,
+            VerifCoverIntrinsicOp, LayerBlockOp, MatchOp, ViewIntrinsicOp>(
             [&](auto opNode) -> ResultType {
               return thisCast->visitStmt(opNode, args...);
             })
@@ -292,6 +292,7 @@ class StmtVisitor {
   HANDLE(UnclockedAssumeIntrinsicOp);
   HANDLE(LayerBlockOp);
   HANDLE(MatchOp);
+  HANDLE(ViewIntrinsicOp);
 
 #undef HANDLE
 };

test/Dialect/FIRRTL/round-trip.mlir

@@ -40,6 +40,35 @@ firrtl.module @Intrinsics(in %ui : !firrtl.uint, in %clock: !firrtl.clock, in %u
   %p = firrtl.int.generic "params" <FORMAT: none = "foobar"> : () -> !firrtl.bundle<x: uint<1>>
   %po = firrtl.int.generic "params_and_operand" <X: i64 = 123> %ui1 : (!firrtl.uint<1>) -> !firrtl.clock
   firrtl.int.generic "inputs" %clock, %ui1, %clock : (!firrtl.clock, !firrtl.uint<1>, !firrtl.clock) -> ()
+
+  %val = firrtl.wire : !firrtl.uint<1>
+  // CHECK: firrtl.view "View"
+  // CHECK-SAME: <{
+  // CHECK-SAME:     elements = [
+  // CHECK-SAME:       {
+  // CHECK-SAME:         class = "sifive.enterprise.grandcentral.AugmentedGroundType",
+  // CHECK-SAME:         name = "baz"
+  // CHECK-SAME:       },
+  // CHECK-SAME:       {
+  // CHECK-SAME:         class = "sifive.enterprise.grandcentral.AugmentedGroundType",
+  // CHECK-SAME:         name = "qux"
+  // CHECK-SAME:       }
+  // CHECK-SAME:     ]
+  // CHECK-SAME: }>, %val, %val : !firrtl.uint<1>, !firrtl.uint<1>
+  firrtl.view "View", <{
+    class = "sifive.enterprise.grandcentral.AugmentedBundleType",
+    defName = "Bar",
+    elements = [
+      {
+        class = "sifive.enterprise.grandcentral.AugmentedGroundType",
+        name = "baz"
+      },
+      {
+        class = "sifive.enterprise.grandcentral.AugmentedGroundType",
+        name = "qux"
+      }
+    ]
+  }>, %val, %val : !firrtl.uint<1>, !firrtl.uint<1>
 }
 
 // CHECK-LABEL: firrtl.module @FPGAProbe