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[RISCV][GISEL] instruction-select vmclr (#110782)
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This is stacked on #110778. This PR adds and tests renderVLOp too, as
that is needed from vmclr.
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@michaelmaitland
michaelmaitland authored Oct 4, 2024
1 parent 78089d5 commit f873fc3
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25 changes: 25 additions & 0 deletions llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
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Expand Up @@ -100,6 +100,8 @@ class RISCVInstructionSelector : public InstructionSelector {
return selectSHXADD_UWOp(Root, ShAmt);
}

ComplexRendererFns renderVLOp(MachineOperand &Root) const;

// Custom renderers for tablegen
void renderNegImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx) const;
Expand Down Expand Up @@ -376,6 +378,29 @@ RISCVInstructionSelector::selectSHXADD_UWOp(MachineOperand &Root,
return std::nullopt;
}

InstructionSelector::ComplexRendererFns
RISCVInstructionSelector::renderVLOp(MachineOperand &Root) const {
assert(Root.isReg() && "Expected operand to be a Register");
MachineInstr *RootDef = MRI->getVRegDef(Root.getReg());

if (RootDef->getOpcode() == TargetOpcode::G_CONSTANT) {
auto C = RootDef->getOperand(1).getCImm();
if (C->getValue().isAllOnes())
// If the operand is a G_CONSTANT with value of all ones it is larger than
// VLMAX. We convert it to an immediate with value VLMaxSentinel. This is
// recognized specially by the vsetvli insertion pass.
return {{[=](MachineInstrBuilder &MIB) {
MIB.addImm(RISCV::VLMaxSentinel);
}}};

if (isUInt<5>(C->getZExtValue())) {
uint64_t ZExtC = C->getZExtValue();
return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(ZExtC); }}};
}
}
return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); }}};
}

InstructionSelector::ComplexRendererFns
RISCVInstructionSelector::selectAddrRegImm(MachineOperand &Root) const {
if (!Root.isReg())
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8 changes: 8 additions & 0 deletions llvm/lib/Target/RISCV/RISCVGISel.td
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Expand Up @@ -50,6 +50,14 @@ def GIAddrRegImm :
GIComplexOperandMatcher<s32, "selectAddrRegImm">,
GIComplexPatternEquiv<AddrRegImm>;

// FIXME: This is labelled as handling 's32', however the ComplexPattern it
// refers to handles both i32 and i64 based on the HwMode. Currently this LLT
// parameter appears to be ignored so this pattern works for both, however we
// should add a LowLevelTypeByHwMode, and use that to define our XLenLLT instead
// here.
def GIVLOp : GIComplexOperandMatcher<s32, "renderVLOp">,
GIComplexPatternEquiv<VLOp>;

// Convert from i32 immediate to i64 target immediate to make SelectionDAG type
// checking happy so we can use ADDIW which expects an XLen immediate.
def as_i64imm : SDNodeXForm<imm, [{
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76 changes: 76 additions & 0 deletions llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv32.mir
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@@ -0,0 +1,76 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
# RUN: -verify-machineinstrs %s -o - | FileCheck %s

---
name: negative_vl
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: negative_vl
; CHECK: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, -2
; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[ADDI]], 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s32) = G_CONSTANT i32 -2
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
$v0 = COPY %1(<vscale x 1 x s1>)
PseudoRET implicit $v0
...
---
name: nonconst_vl
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $x10
; CHECK-LABEL: name: nonconst_vl
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[COPY]], 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s32) = COPY $x10
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
$v0 = COPY %1(<vscale x 1 x s1>)
PseudoRET implicit $v0
...

---
name: nonzero_vl
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: nonzero_vl
; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s32) = G_CONSTANT i32 1
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
$v0 = COPY %1(<vscale x 1 x s1>)
PseudoRET implicit $v0
...

---
name: zero_vl
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: zero_vl
; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 0, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s32) = G_CONSTANT i32 0
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
$v0 = COPY %1(<vscale x 1 x s1>)
PseudoRET implicit $v0
...

76 changes: 76 additions & 0 deletions llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv64.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=riscv64 -mattr=+v,+m -run-pass=instruction-select \
# RUN: -verify-machineinstrs %s -o - | FileCheck %s

---
name: negative_vl
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: negative_vl
; CHECK: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, -2
; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[ADDI]], 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s64) = G_CONSTANT i64 -2
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
$v0 = COPY %1(<vscale x 1 x s1>)
PseudoRET implicit $v0
...
---
name: nonconst_vl
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $x10
; CHECK-LABEL: name: nonconst_vl
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[COPY]], 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s64) = COPY $x10
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
$v0 = COPY %1(<vscale x 1 x s1>)
PseudoRET implicit $v0
...

---
name: nonzero_vl
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: nonzero_vl
; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s64) = G_CONSTANT i64 1
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
$v0 = COPY %1(<vscale x 1 x s1>)
PseudoRET implicit $v0
...

---
name: zero_vl
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: zero_vl
; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 0, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s64) = G_CONSTANT i64 0
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
$v0 = COPY %1(<vscale x 1 x s1>)
PseudoRET implicit $v0
...

124 changes: 124 additions & 0 deletions llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir
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@@ -0,0 +1,124 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s

---
name: splat_zero_nxv1i1
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splat_zero_nxv1i1
; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s32) = G_CONSTANT i32 -1
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
$v0 = COPY %1(<vscale x 1 x s1>)
PseudoRET implicit $v0
...
---
name: splat_zero_nxv2i1
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splat_zero_nxv2i1
; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s32) = G_CONSTANT i32 -1
%1:vrb(<vscale x 2 x s1>) = G_VMCLR_VL %0(s32)
$v0 = COPY %1(<vscale x 2 x s1>)
PseudoRET implicit $v0
...
---
name: splat_zero_nxv4i1
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splat_zero_nxv4i1
; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s32) = G_CONSTANT i32 -1
%1:vrb(<vscale x 4 x s1>) = G_VMCLR_VL %0(s32)
$v0 = COPY %1(<vscale x 4 x s1>)
PseudoRET implicit $v0
...
---
name: splat_zero_nxv8i1
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splat_zero_nxv8i1
; CHECK: [[PseudoVMCLR_M_B8_:%[0-9]+]]:vr = PseudoVMCLR_M_B8 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B8_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s32) = G_CONSTANT i32 -1
%1:vrb(<vscale x 8 x s1>) = G_VMCLR_VL %0(s32)
$v0 = COPY %1(<vscale x 8 x s1>)
PseudoRET implicit $v0
...
---
name: splat_zero_nxv16i1
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splat_zero_nxv16i1
; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s32) = G_CONSTANT i32 -1
%1:vrb(<vscale x 16 x s1>) = G_VMCLR_VL %0(s32)
$v0 = COPY %1(<vscale x 16 x s1>)
PseudoRET implicit $v0
...
---
name: splat_zero_nxv32i1
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splat_zero_nxv32i1
; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s32) = G_CONSTANT i32 -1
%1:vrb(<vscale x 32 x s1>) = G_VMCLR_VL %0(s32)
$v0 = COPY %1(<vscale x 32 x s1>)
PseudoRET implicit $v0
...
---
name: splat_zero_nxv64i1
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splat_zero_nxv64i1
; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s32) = G_CONSTANT i32 -1
%1:vrb(<vscale x 64 x s1>) = G_VMCLR_VL %0(s32)
$v0 = COPY %1(<vscale x 64 x s1>)
PseudoRET implicit $v0
...

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