[RISCV][GISEL] Generate VLMax using -1 constant #110778
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@llvm/pr-subscribers-llvm-globalisel @llvm/pr-subscribers-backend-risc-v Author: Michael Maitland (michaelmaitland) ChangesSelectionDAG uses ISD::REGISTER and uses RISCV::X0 to represent VLMAX. Then in ComplexPattern VLOpt uses selectVLOp to convert RISCV::X0 to RISCV::VLMaxSentinel. The original legalization patch for G_SPLAT_VECTOR used Register RISCV::X0 directly. $x0 has no LLT type, so GIComplexOperandMatcher has no way of matching. The approach we are changing to here will allow us to successfully use GIComplexOperandMatcher to implement the ComplexMatcherFn selectVLOp in GISEL since the operand now has a type. Patch is 20.27 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/110778.diff 3 Files Affected:
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index e82d353953a5e1..9b63518e762226 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -859,19 +859,21 @@ static MachineInstrBuilder buildAllOnesMask(LLT VecTy, const SrcOp &VL,
/// Gets the two common "VL" operands: an all-ones mask and the vector length.
/// VecTy is a scalable vector type.
-static std::pair<MachineInstrBuilder, Register>
+static std::pair<MachineInstrBuilder, MachineInstrBuilder>
buildDefaultVLOps(const DstOp &Dst, MachineIRBuilder &MIB,
MachineRegisterInfo &MRI) {
LLT VecTy = Dst.getLLTTy(MRI);
assert(VecTy.isScalableVector() && "Expecting scalable container type");
- Register VL(RISCV::X0);
- MachineInstrBuilder Mask = buildAllOnesMask(VecTy, VL, MIB, MRI);
+ const RISCVSubtarget &STI = MIB.getMF().getSubtarget<RISCVSubtarget>();
+ LLT XLenTy(STI.getXLenVT());
+ auto VL = MIB.buildConstant(XLenTy, RISCV::VLMaxSentinel);
+ auto Mask = buildAllOnesMask(VecTy, VL, MIB, MRI);
return {Mask, VL};
}
static MachineInstrBuilder
buildSplatPartsS64WithVL(const DstOp &Dst, const SrcOp &Passthru, Register Lo,
- Register Hi, Register VL, MachineIRBuilder &MIB,
+ Register Hi, const SrcOp &VL, MachineIRBuilder &MIB,
MachineRegisterInfo &MRI) {
// TODO: If the Hi bits of the splat are undefined, then it's fine to just
// splat Lo even if it might be sign extended. I don't think we have
@@ -887,7 +889,7 @@ buildSplatPartsS64WithVL(const DstOp &Dst, const SrcOp &Passthru, Register Lo,
static MachineInstrBuilder
buildSplatSplitS64WithVL(const DstOp &Dst, const SrcOp &Passthru,
- const SrcOp &Scalar, Register VL,
+ const SrcOp &Scalar, const SrcOp &VL,
MachineIRBuilder &MIB, MachineRegisterInfo &MRI) {
assert(Scalar.getLLTTy(MRI) == LLT::scalar(64) && "Unexpected VecTy!");
auto Unmerge = MIB.buildUnmerge(LLT::scalar(32), Scalar);
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv32.mir
index 109536a07d5ec1..d14257e2794e6f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv32.mir
@@ -8,8 +8,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv1i1_0
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMCLR_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMCLR_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 1 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 0
@@ -25,8 +26,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv1i1_1
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 1 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 1
@@ -70,8 +72,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv2i1_0
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMCLR_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMCLR_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 2 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 0
@@ -87,8 +90,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv2i1_1
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 2 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 1
@@ -132,8 +136,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv4i1_0
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMCLR_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMCLR_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 4 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 0
@@ -149,8 +154,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv4i1_1
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 4 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 1
@@ -194,8 +200,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv8i1_0
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMCLR_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMCLR_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 8 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 0
@@ -211,8 +218,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv8i1_1
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 8 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 1
@@ -256,8 +264,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv16i1_0
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMCLR_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMCLR_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 16 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 0
@@ -273,8 +282,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv16i1_1
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 16 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 1
@@ -318,8 +328,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv32i1_0
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMCLR_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMCLR_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 32 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 0
@@ -335,8 +346,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv32i1_1
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 32 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 1
@@ -380,8 +392,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv64i1_0
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMCLR_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMCLR_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 64 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 0
@@ -397,8 +410,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv64i1_1
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 64 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 1
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv64.mir
index 7bf5f83dd91445..5210a7e035717e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv64.mir
@@ -8,8 +8,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv1i1_0
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMCLR_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMCLR_VL [[C]](s64)
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 1 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 0
@@ -25,8 +26,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv1i1_1
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s64)
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 1 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 1
@@ -73,8 +75,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv2i1_0
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMCLR_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMCLR_VL [[C]](s64)
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 2 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 0
@@ -90,8 +93,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv2i1_1
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s64)
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 2 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 1
@@ -138,8 +142,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv4i1_0
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMCLR_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMCLR_VL [[C]](s64)
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 4 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 0
@@ -155,8 +160,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv4i1_1
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s64)
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 4 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 1
@@ -203,8 +209,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv8i1_0
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMCLR_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMCLR_VL [[C]](s64)
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 8 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 0
@@ -220,8 +227,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv8i1_1
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C]](s64)
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 8 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 1
@@ -268,8 +276,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv16i1_0
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMCLR_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMCLR_VL [[C]](s64)
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 16 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 0
@@ -285,8 +294,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv16i1_1
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL [[C]](s64)
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 16 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 1
@@ -333,8 +343,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv32i1_0
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMCLR_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMCLR_VL [[C]](s64)
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 32 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 0
@@ -350,8 +361,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv32i1_1
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL [[C]](s64)
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 32 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 1
@@ -398,8 +410,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv64i1_0
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMCLR_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMCLR_VL [[C]](s64)
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 64 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 0
@@ -415,8 +428,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv64i1_1
- ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL $x0
- ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]...
[truncated]
|
topperc
reviewed
Oct 2, 2024
| MachineInstrBuilder Mask = buildAllOnesMask(VecTy, VL, MIB, MRI); | ||
| const RISCVSubtarget &STI = MIB.getMF().getSubtarget<RISCVSubtarget>(); | ||
| LLT XLenTy(STI.getXLenVT()); | ||
| auto VL = MIB.buildConstant(XLenTy, RISCV::VLMaxSentinel); |
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This should be -1 not VLMaxSentinel. VLMaxSentinel encoding belongs to RISCV post-isel instructions. The specific value could be any value other than 0-31 since those are the only immediate values allowed post-isel.
The constant created here is a pre-isel value and we need it be a value larger than vlmax which can be as large as 65536. vmclr_vl/vmset_vl/etc. will eventually be provided VLs that come from users.
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SelectionDAG uses ISD::REGISTER and uses RISCV::X0 to represent VLMAX. Then in ComplexPattern VLOpt uses selectVLOp to convert RISCV::X0 to RISCV::VLMaxSentinel. The original legalization patch for G_SPLAT_VECTOR used Register RISCV::X0 directly. $x0 has no LLT type, so GIComplexOperandMatcher has no way of matching. The approach we are changing to here will allow us to successfully use GIComplexOperandMatcher to implement the ComplexMatcherFn selectVLOp in GISEL.
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SelectionDAG uses ISD::REGISTER and uses RISCV::X0 to represent VLMAX. Then in ComplexPattern VLOpt uses selectVLOp to convert RISCV::X0 to RISCV::VLMaxSentinel. The original legalization patch for G_SPLAT_VECTOR used Register RISCV::X0 directly. $x0 has no LLT type, so GIComplexOperandMatcher has no way of matching. The approach we are changing to here will allow us to successfully use GIComplexOperandMatcher to implement the ComplexMatcherFn selectVLOp in GISEL since the operand now has a type.
xgupta
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SelectionDAG uses ISD::REGISTER and uses RISCV::X0 to represent VLMAX. Then in ComplexPattern VLOpt uses selectVLOp to convert RISCV::X0 to RISCV::VLMaxSentinel. The original legalization patch for G_SPLAT_VECTOR used Register RISCV::X0 directly. $x0 has no LLT type, so GIComplexOperandMatcher has no way of matching. The approach we are changing to here will allow us to successfully use GIComplexOperandMatcher to implement the ComplexMatcherFn selectVLOp in GISEL since the operand now has a type.
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This is stacked on #110778. This PR adds and tests renderVLOp too, as that is needed from vmclr.
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SelectionDAG uses ISD::REGISTER and uses RISCV::X0 to represent VLMAX. Then in ComplexPattern VLOpt uses selectVLOp to convert RISCV::X0 to RISCV::VLMaxSentinel.
The original legalization patch for G_SPLAT_VECTOR used Register RISCV::X0 directly. $x0 has no LLT type, so GIComplexOperandMatcher has no way of matching.
The approach we are changing to here will allow us to successfully use GIComplexOperandMatcher to implement the ComplexMatcherFn selectVLOp in GISEL since the operand now has a type.