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[RISCV][GISEL] Generate VLMax using -1 constant #110778

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merged 4 commits into from
Oct 2, 2024
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[RISCV][GISEL] Generate VLMax using -1 constant #110778

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c945843
[RISCV][GISEL] Generate VLMax using RISCV::VLMaxSentinel
michaelmaitland Oct 2, 2024
4a64ebe
fixup! update regbank tests
michaelmaitland Oct 2, 2024
d58058e
fixup! fix more tests
michaelmaitland Oct 2, 2024
1a23dc7
fixup! don't use VLMaxSentinel
michaelmaitland Oct 2, 2024
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12 changes: 7 additions & 5 deletions llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -833,19 +833,21 @@ static MachineInstrBuilder buildAllOnesMask(LLT VecTy, const SrcOp &VL,

/// Gets the two common "VL" operands: an all-ones mask and the vector length.
/// VecTy is a scalable vector type.
static std::pair<MachineInstrBuilder, Register>
static std::pair<MachineInstrBuilder, MachineInstrBuilder>
buildDefaultVLOps(const DstOp &Dst, MachineIRBuilder &MIB,
MachineRegisterInfo &MRI) {
LLT VecTy = Dst.getLLTTy(MRI);
assert(VecTy.isScalableVector() && "Expecting scalable container type");
Register VL(RISCV::X0);
MachineInstrBuilder Mask = buildAllOnesMask(VecTy, VL, MIB, MRI);
const RISCVSubtarget &STI = MIB.getMF().getSubtarget<RISCVSubtarget>();
LLT XLenTy(STI.getXLenVT());
auto VL = MIB.buildConstant(XLenTy, -1);
auto Mask = buildAllOnesMask(VecTy, VL, MIB, MRI);
return {Mask, VL};
}

static MachineInstrBuilder
buildSplatPartsS64WithVL(const DstOp &Dst, const SrcOp &Passthru, Register Lo,
Register Hi, Register VL, MachineIRBuilder &MIB,
Register Hi, const SrcOp &VL, MachineIRBuilder &MIB,
MachineRegisterInfo &MRI) {
// TODO: If the Hi bits of the splat are undefined, then it's fine to just
// splat Lo even if it might be sign extended. I don't think we have
Expand All @@ -861,7 +863,7 @@ buildSplatPartsS64WithVL(const DstOp &Dst, const SrcOp &Passthru, Register Lo,

static MachineInstrBuilder
buildSplatSplitS64WithVL(const DstOp &Dst, const SrcOp &Passthru,
const SrcOp &Scalar, Register VL,
const SrcOp &Scalar, const SrcOp &VL,
MachineIRBuilder &MIB, MachineRegisterInfo &MRI) {
assert(Scalar.getLLTTy(MRI) == LLT::scalar(64) && "Unexpected VecTy!");
auto Unmerge = MIB.buildUnmerge(LLT::scalar(32), Scalar);
Expand Down
5 changes: 3 additions & 2 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-constbarrier-rv32.mir
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Expand Up @@ -52,8 +52,9 @@ name: constbarrier_nxv2i1
body: |
bb.0.entry:
; CHECK-LABEL: name: constbarrier_nxv2i1
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMCLR_VL $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMCLR_VL [[C]](s32)
; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(<vscale x 2 x s1>) = G_CONSTANT_FOLD_BARRIER [[VMCLR_VL]]
; CHECK-NEXT: $v8 = COPY [[CONSTANT_FOLD_BARRIER]](<vscale x 2 x s1>)
; CHECK-NEXT: PseudoRET implicit $v8
Expand Down
5 changes: 3 additions & 2 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-constbarrier-rv64.mir
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Expand Up @@ -70,8 +70,9 @@ name: constbarrier_nxv2i1
body: |
bb.0.entry:
; CHECK-LABEL: name: constbarrier_nxv2i1
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMCLR_VL $x0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s64)
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMCLR_VL [[C]](s64)
; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(<vscale x 2 x s1>) = G_CONSTANT_FOLD_BARRIER [[VMCLR_VL]]
; CHECK-NEXT: $v8 = COPY [[CONSTANT_FOLD_BARRIER]](<vscale x 2 x s1>)
; CHECK-NEXT: PseudoRET implicit $v8
Expand Down
86 changes: 50 additions & 36 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-extract-subvector.mir
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70 changes: 42 additions & 28 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv32.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -8,8 +8,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv1i1_0
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMCLR_VL $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMCLR_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 1 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 0
Expand All @@ -25,8 +26,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv1i1_1
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 1 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 1
Expand Down Expand Up @@ -69,8 +71,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv2i1_0
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMCLR_VL $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMCLR_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 2 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 0
Expand All @@ -86,8 +89,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv2i1_1
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 2 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 1
Expand Down Expand Up @@ -130,8 +134,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv4i1_0
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL $x0
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMCLR_VL $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMCLR_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 4 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 0
Expand All @@ -147,8 +152,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv4i1_1
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL $x0
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 4 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 1
Expand Down Expand Up @@ -191,8 +197,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv8i1_0
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL $x0
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMCLR_VL $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMCLR_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 8 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 0
Expand All @@ -208,8 +215,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv8i1_1
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL $x0
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 8 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 1
Expand Down Expand Up @@ -252,8 +260,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv16i1_0
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL $x0
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMCLR_VL $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMCLR_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 16 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 0
Expand All @@ -269,8 +278,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv16i1_1
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL $x0
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 16 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 1
Expand Down Expand Up @@ -313,8 +323,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv32i1_0
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL $x0
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMCLR_VL $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMCLR_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 32 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 0
Expand All @@ -330,8 +341,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv32i1_1
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL $x0
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 32 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 1
Expand Down Expand Up @@ -374,8 +386,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv64i1_0
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL $x0
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMCLR_VL $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMCLR_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 64 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 0
Expand All @@ -391,8 +404,9 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: splatvector_nxv64i1_1
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL $x0
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL [[C]](s32)
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 64 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(s1) = G_CONSTANT i1 1
Expand Down
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