Fix stm32-rs#34

luctius · Dec 13, 2021 · ae5f7cf · ae5f7cf
1 parent d30e860
commit ae5f7cf
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Showing 3 changed files with 5 additions and 3 deletions.
diff --git a/src/fdcan.rs b/src/fdcan.rs
@@ -1391,6 +1391,7 @@ where
         // Check if there is a request pending to abort
         if self.has_pending_frame(idx) {
             let idx: u8 = idx.into();
+            let idx = 1u8 << idx;
 
             // Abort Request
             can.txbcr.write(|w| unsafe { w.cr().bits(idx) });
@@ -1411,6 +1412,7 @@ where
     fn has_pending_frame(&self, idx: Mailbox) -> bool {
         let can = self.registers();
         let idx: u8 = idx.into();
+        let idx = 1u8 << idx;
 
         can.txbrp.read().trp().bits() & idx != 0
     }

diff --git a/src/fdcan/filter.rs b/src/fdcan/filter.rs
@@ -37,7 +37,7 @@ impl StandardFilter {
                 filter: 0x0,
                 mask: 0x0,
             },
-            action: Action::StoreInFifo0,
+            action: Action::StoreInFifo1,
         }
     }
 
@@ -80,7 +80,7 @@ impl ExtendedFilter {
                 filter: 0x0,
                 mask: 0x0,
             },
-            action: Action::StoreInFifo0,
+            action: Action::StoreInFifo1,
         }
     }
 

diff --git a/src/fdcan/message_ram/txbuffer_element.rs b/src/fdcan/message_ram/txbuffer_element.rs
@@ -127,7 +127,7 @@ impl<'a> ID_W<'a> {
     #[inline(always)]
     #[allow(dead_code)]
     pub unsafe fn bits(self, value: u32) -> &'a mut W {
-        self.w.bits[0] = (self.w.bits[0] & !(0x0FFFFFFF)) | ((value as u32) & 0x0FFFFFFF);
+        self.w.bits[0] = (self.w.bits[0] & !(0x1FFFFFFF)) | ((value as u32) & 0x1FFFFFFF);
         self.w
     }
 }