feat: single page index scan with predicate (#58)

* feat: sorted_limbs chip checking each limb less than limb_bits bits

* feat: completed sorted_limbs chip with tests

* feat: SortedLimbsChip with LessThan subchip

* feat: less_than subchip refactored

* feat: rename SortedLimbsChip to AssertSortedChip and write LessThanChip tests

* chore: change name of assert sorted chip

* chore: fix names in tests for AssertSortedChip

* chore: address comments

* chore: cleanup

* chore: change MAX from generic to instance field for LessThanChip and AssertSortedChip

* feat: IsLessThanChip to compare two numbers

* feat: IsLessThanTuple subchip for different limb_bits

* feat: IsLessThanTupleChip subchip in AssertSortedChip

* chore: address comments first pass

* chore: refactor AssertSorted, IsEqual, IsLessThan, and IsLessThanTuple chips

* chore: address comments

* chore: eliminate high dim poly from IsLessThanTupleChip

* chore: fix tests

* chore: address comments for AssertSortedChip

* chore: cleanup AssertSorted

* chore: cleanup

* chore: include roundtrip flatten and from_slice tests

* feat: flatten and from_slice for IO and Aux columns

* create files

* chore: begin PageIndexScanChip

* feat: prototype

* feat: rename Chip to AirBridge

* feat: single page index scan chip for less than predicate

* feat: partitioned main

* chore: cleanup index scan for less than predicate

* feat: x as public value

* feat: page index scan with comparator enum

* feat: page index scan for greater than predicate

* feat: page index scan for equal to predicates

* feat: page index scan for less than or equal to predicate

* feat: page index scan for greater than or equal to predicate

* chore: cleanup some branches

* chore: refactor code to reduce repetition

* chore: cleanup PageIndexScanInputChip

* chore: fix test

* merge IsEqualVec columns

* remove range_max from PageIndexScan chips

* chore: address comments

* feat: use FinalPage

* chore: refactor index_scan_test

* chore: address comments

chips/src/is_equal_vec/columns.rs

@@ -6,18 +6,21 @@ pub struct IsEqualVecIOCols<T> {
 }
 
 impl<T: Clone> IsEqualVecIOCols<T> {
-    pub fn new(x: Vec<T>, y: Vec<T>, prod: T) -> Self {
-        Self { x, y, prod }
+    pub fn flatten(&self) -> Vec<T> {
+        let mut res: Vec<T> = self.x.iter().chain(self.y.iter()).cloned().collect();
+        res.push(self.prod.clone());
+        res
     }
 
-    // Note that the slice this function takes is of an unusual
-    // slc should be a whole row of the trace
     pub fn from_slice(slc: &[T], vec_len: usize) -> Self {
-        Self {
-            x: slc[0..vec_len].to_vec(),
-            y: slc[vec_len..2 * vec_len].to_vec(),
-            prod: slc[3 * vec_len - 1].clone(),
-        }
+        let x = slc[0..vec_len].to_vec();
+        let y = slc[vec_len..2 * vec_len].to_vec();
+        let prod = slc[2 * vec_len].clone();
+        Self { x, y, prod }
+    }
+
+    pub fn get_width(vec_len: usize) -> usize {
+        vec_len + vec_len + 1
     }
 }
 
@@ -28,19 +31,18 @@ pub struct IsEqualVecAuxCols<T> {
 }
 
 impl<T: Clone> IsEqualVecAuxCols<T> {
-    pub fn new(prods: Vec<T>, invs: Vec<T>) -> Self {
-        Self { prods, invs }
+    pub fn flatten(&self) -> Vec<T> {
+        self.prods.iter().chain(self.invs.iter()).cloned().collect()
     }
 
     pub fn from_slice(slc: &[T], vec_len: usize) -> Self {
-        Self {
-            prods: slc[0..vec_len].to_vec(),
-            invs: slc[vec_len..2 * vec_len].to_vec(),
-        }
+        let prods = slc[0..vec_len].to_vec();
+        let invs = slc[vec_len..2 * vec_len].to_vec();
+        Self { prods, invs }
     }
 
-    pub fn flatten(&self) -> Vec<T> {
-        self.prods.iter().chain(self.invs.iter()).cloned().collect()
+    pub fn get_width(vec_len: usize) -> usize {
+        vec_len + vec_len
     }
 }
 
@@ -63,9 +65,15 @@ impl<T: Clone> IsEqualVecCols<T> {
     }
 
     pub fn from_slice(slc: &[T], vec_len: usize) -> Self {
+        let x = slc[0..vec_len].to_vec();
+        let y = slc[vec_len..2 * vec_len].to_vec();
+        let prod = slc[3 * vec_len - 1].clone();
+        let prods = slc[2 * vec_len..3 * vec_len].to_vec();
+        let invs = slc[3 * vec_len..4 * vec_len].to_vec();
+
         Self {
-            io: IsEqualVecIOCols::from_slice(slc, vec_len),
-            aux: IsEqualVecAuxCols::from_slice(&slc[2 * vec_len..], vec_len),
+            io: IsEqualVecIOCols { x, y, prod },
+            aux: IsEqualVecAuxCols { prods, invs },
         }
     }
 
@@ -74,7 +82,8 @@ impl<T: Clone> IsEqualVecCols<T> {
             .x
             .iter()
             .chain(self.io.y.iter())
-            .chain(self.aux.flatten().iter())
+            .chain(self.aux.prods.iter())
+            .chain(self.aux.invs.iter())
             .cloned()
             .collect()
     }

chips/src/lib.rs

@@ -15,6 +15,7 @@ pub mod page_rw_checker;
 /// Chip to range check a value has less than a fixed number of bits
 pub mod range;
 pub mod range_gate;
+pub mod single_page_index_scan;
 pub mod sub_chip;
 pub mod sum;
 mod utils;

chips/src/range_gate/mod.rs

@@ -36,6 +36,10 @@ impl RangeCheckerGateChip {
         }
     }
 
+    pub fn bus_index(&self) -> usize {
+        self.air.bus_index
+    }
+
     pub fn range_max(&self) -> u32 {
         self.air.range_max
     }

chips/src/single_page_index_scan/mod.rs

@@ -0,0 +1,6 @@
+pub mod page_controller;
+pub mod page_index_scan_input;
+pub mod page_index_scan_output;
+
+#[cfg(test)]
+pub mod tests;