Updated to add:

Fabric DMA controller Additional fabric SRAM connected to PCIe CoreGPIO connected to FIC3 via CoreAPB3 CoreRESET_1 to reset CoreGPIO synchroniously to the FIC3 clock Addional AXI4 interconnect to connect DMA to FIC1 Changed AND3 to AND4 to connect the FIC1 DLL Lock signal Tested eMMC and SD card versions building, changes verified by apps
polarfire-soc · Nov 11, 2020 · 08b9aef · 08b9aef
1 parent ecf2db0
commit 08b9aef
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Showing 10 changed files with 1,845 additions and 33 deletions.
diff --git a/script_support/MPFS_ICICLE_SD_CARD_recursive.tcl b/script_support/MPFS_ICICLE_SD_CARD_recursive.tcl
@@ -21,6 +21,10 @@ source script_support/components/PF_PCIE_C0.tcl
 source script_support/components/PF_TX_PLL_C0.tcl 
 source script_support/components/PF_XCVR_REF_CLK_C0.tcl 
 source script_support/components/LSRAM_0.tcl 
+source script_support/components/COREAXI4DMACONTROLLER.tcl
+source script_support/components/COREAXI4INTERCONNECT.tcl
+source script_support/components/GPIO.tcl
+source script_support/components/CoreAPB3.tcl
 source script_support/components/PCIE_BASE.tcl 
 source script_support/components/MPFS_ICICLE_SD_CARD.tcl 
 build_design_hierarchy
diff --git a/script_support/MPFS_ICICLE_eMMC_recursive.tcl b/script_support/MPFS_ICICLE_eMMC_recursive.tcl
@@ -21,6 +21,10 @@ source script_support/components/PF_PCIE_C0.tcl
 source script_support/components/PF_TX_PLL_C0.tcl 
 source script_support/components/PF_XCVR_REF_CLK_C0.tcl 
 source script_support/components/LSRAM_0.tcl 
+source script_support/components/COREAXI4DMACONTROLLER.tcl
+source script_support/components/COREAXI4INTERCONNECT.tcl
+source script_support/components/GPIO.tcl
+source script_support/components/CoreAPB3.tcl
 source script_support/components/PCIE_BASE.tcl 
 source script_support/components/MPFS_ICICLE_eMMC.tcl 
 build_design_hierarchy
diff --git a/script_support/PF_SoC_MSS_Icicle_SD.cfg b/script_support/PF_SoC_MSS_Icicle_SD.cfg
@@ -140,7 +140,7 @@ FIC_0_AXI4_MASTER_USED                              true
 FIC_0_AXI4_SLAVE_USED                               true
 FIC_0_EMBEDDED_DLL_USED                             true
 FIC_1_AXI4_MASTER_USED                              false
-FIC_1_AXI4_SLAVE_USED                               false
+FIC_1_AXI4_SLAVE_USED                               true
 FIC_1_EMBEDDED_DLL_USED                             true
 FIC_2_AXI4_SLAVE_USED                               false
 FIC_2_EMBEDDED_DLL_USED                             true

diff --git a/script_support/PF_SoC_MSS_Icicle_eMMC.cfg b/script_support/PF_SoC_MSS_Icicle_eMMC.cfg
@@ -140,7 +140,7 @@ FIC_0_AXI4_MASTER_USED                              true
 FIC_0_AXI4_SLAVE_USED                               true
 FIC_0_EMBEDDED_DLL_USED                             true
 FIC_1_AXI4_MASTER_USED                              false
-FIC_1_AXI4_SLAVE_USED                               false
+FIC_1_AXI4_SLAVE_USED                               true
 FIC_1_EMBEDDED_DLL_USED                             true
 FIC_2_AXI4_SLAVE_USED                               false
 FIC_2_EMBEDDED_DLL_USED                             true

diff --git a/script_support/TCL_PARAMETERS_BASE_DESIGN.tcl b/script_support/TCL_PARAMETERS_BASE_DESIGN.tcl
diff --git a/script_support/components/COREAXI4DMACONTROLLER.tcl b/script_support/components/COREAXI4DMACONTROLLER.tcl
@@ -0,0 +1,5 @@
+# Exporting Component Description of COREAXI4DMACONTROLLER_C0 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS250T_ES-FCVG484E
+# Create and Configure the core component COREAXI4DMACONTROLLER_C0
+create_and_configure_core -core_vlnv {Actel:DirectCore:COREAXI4DMACONTROLLER:2.0.100} -component_name {DMACONTROLLER} -params $DMA_param
diff --git a/script_support/components/COREAXI4INTERCONNECT.tcl b/script_support/components/COREAXI4INTERCONNECT.tcl
@@ -0,0 +1,5 @@
+# Exporting core COREAXI4INTERCONNECT_C0 to TCL
+# Exporting Create design command for core COREAXI4INTERCONNECT_C0
+create_and_configure_core -core_vlnv {Actel:DirectCore:COREAXI4INTERCONNECT:2.8.103} -component_name {AXI4INTERCONNECT} -params $AXI4Interconnect_param
+
+# Exporting core COREAXI4INTERCONNECT_C0 to TCL done
diff --git a/script_support/components/CoreAPB3.tcl b/script_support/components/CoreAPB3.tcl
@@ -0,0 +1,6 @@
+# Exporting Component Description of CoreAPB3_C0 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS250T_ES-FCVG484E
+# Create and Configure the core component CoreAPB3_C0
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.1.100} -component_name {APB3} -params $CoreAPB3_param
+# Exporting Component Description of CoreAPB3_C0 to TCL done
diff --git a/script_support/components/GPIO.tcl b/script_support/components/GPIO.tcl
@@ -0,0 +1,7 @@
+# Exporting Component Description of CoreGPIO_C0 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS250T_ES-FCVG484E
+# Create and Configure the core component CoreGPIO_C0
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {GPIO} -params $CoreGPIO_param
+
+# Exporting Component Description of CoreGPIO_C0 to TCL done
diff --git a/script_support/components/MPFS_ICICLE_BASE_DESIGN.tcl b/script_support/components/MPFS_ICICLE_BASE_DESIGN.tcl
@@ -93,12 +93,17 @@ sd_create_bus_port -sd_name ${sd_name} -port_name {DQS} -port_direction {INOUT}
 sd_create_bus_port -sd_name ${sd_name} -port_name {DQS_N} -port_direction {INOUT} -port_range {[3:0]}
 sd_create_bus_port -sd_name ${sd_name} -port_name {DM} -port_direction {OUT} -port_range {[3:0]}
 
-# Add AND3_0 instance
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND3} -instance_name {AND3_0}
+# Add AND4_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND4} -instance_name {AND4_0}
 
+# Add CORERESET_0 instance
 sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET} -instance_name {CORERESET_0} 
 sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_0:PLL_POWERDOWN_B}
 
+# Add CORERESET_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET} -instance_name {CORERESET_1} 
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_1:PLL_POWERDOWN_B}
+
 # Add INIT_MONITOR instance
 sd_instantiate_component -sd_name ${sd_name} -component_name {INIT_MONITOR} -instance_name {INIT_MONITOR}
 sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR:USRAM_INIT_DONE}
@@ -117,8 +122,9 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR:AUTOCALIB_DONE}
 sd_instantiate_component -sd_name ${sd_name} -component_name {ICICLE_MSS} -instance_name {MSS}
 sd_create_pin_slices -sd_name ${sd_name} -pin_name {MSS:MSS_INT_F2M} -pin_slices {[0]}
 sd_create_pin_slices -sd_name ${sd_name} -pin_name {MSS:MSS_INT_F2M} -pin_slices {[1]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {MSS:MSS_INT_F2M} -pin_slices {[63:2]}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MSS:MSS_INT_F2M[63:2]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MSS:MSS_INT_F2M} -pin_slices {[2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MSS:MSS_INT_F2M} -pin_slices {[63:3]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MSS:MSS_INT_F2M[63:3]} -value {GND}
 sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:MMUART_0_TXD_OE_M2F}
 sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:MMUART_1_TXD_OE_M2F}
 sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MSS:MAC_0_TSU_SOF_TX_M2F}
@@ -165,22 +171,35 @@ sd_instantiate_component -sd_name ${sd_name} -component_name {PCIE_AXI_1} -insta
 # Add LSRAM_0 instance
 sd_instantiate_component -sd_name ${sd_name} -component_name {LSRAM} -instance_name {LSRAM_0}
 
+# Add LSRAM_1 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {LSRAM} -instance_name {LSRAM_1}
+
 # Add PCIE_BASE_0 instance
 sd_instantiate_component -sd_name ${sd_name} -component_name {PCIE_BASE} -instance_name {PCIE_BASE_0}
 sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PCIE_BASE_0:PCIE_1_INTERRUPT} -value {GND}
 
+# Add COREAXI4DMACONTROLLER instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {DMACONTROLLER} -instance_name {COREAXI4DMACONTROLLER_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREAXI4DMACONTROLLER_0:STRTDMAOP} -value {GND}
+
+# Add AXI4INTERCONNECT instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {AXI4INTERCONNECT} -instance_name {COREAXI4INTERCONNECT_0}
+
+# Add COREAPB3 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {APB3} -instance_name {COREABP3_C0}
+
+# Add COREGPIO instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {GPIO} -instance_name {COREGPIO_C0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREGPIO_C0:GPIO_IN} -value {GND}
+
 # Add scalar net connections
-sd_connect_pins -sd_name ${sd_name} -pin_names {"AND3_0:Y" "CORERESET_0:PLL_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:Y" "CORERESET_0:PLL_LOCK"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:FIC_3_DLL_LOCK_M2F" "CORERESET_1:PLL_LOCK"}
 sd_connect_pins -sd_name ${sd_name} -pin_names {"CK" "MSS:CK" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"CK_N" "MSS:CK_N" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"CKE" "MSS:CKE" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {\
-	"CORERESET_0:FABRIC_RESET_N" \
-	"PCIE_AXI_0_0:ARESETN" \
-	"PCIE_AXI_1_0:ARESETN" \
-	"PCIE_BASE_0:PRESETN" \
-	"USB_ULPI_RESET" \
-	"LSRAM_0:ARESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_0:FABRIC_RESET_N" "PCIE_AXI_0_0:ARESETN" "PCIE_AXI_1_0:ARESETN" "PCIE_BASE_0:PRESETN" "USB_ULPI_RESET" "LSRAM_0:ARESETN" "LSRAM_1:ARESETN" "COREAXI4DMACONTROLLER_0:RESETN" "COREAXI4INTERCONNECT_0:ARESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_1:FABRIC_RESET_N" "COREGPIO_C0:PRESETN"}
 sd_connect_pins -sd_name ${sd_name} -pin_names {"CS" "MSS:CS" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"I2C_1_SCL" "MSS:I2C_1_SCL" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"I2C_1_SDA" "MSS:I2C_1_SDA" }
@@ -202,9 +221,10 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"MMUART_3_TXD_M2F" "MSS:MMUART_3
 sd_connect_pins -sd_name ${sd_name} -pin_names {"OR2_1:B" "MSS:GPIO_2_M2F_26" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"OR2_2:B" "MSS:GPIO_2_M2F_27" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"OR2_0:B" "MSS:GPIO_2_M2F_28" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"AND3_0:C" "PCIE_BASE_0:PCIE_PLL_LOCK" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"AND3_0:B" "MSS:FIC_3_DLL_LOCK_M2F" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"AND3_0:A" "MSS:FIC_0_DLL_LOCK_M2F" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:D" "MSS:FIC_1_DLL_LOCK_M2F" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:C" "PCIE_BASE_0:PCIE_PLL_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:B" "MSS:FIC_3_DLL_LOCK_M2F" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:A" "MSS:FIC_0_DLL_LOCK_M2F" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"ODT" "MSS:ODT" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"OR2_0:Y" "MSS:MSS_INT_F2M[0]" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_BASE_0:PCIE_ROOTPORT_INTERRUPT" "MSS:MSS_INT_F2M[1]" }
@@ -230,8 +250,8 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIESS_LANE_TXD2_N" "PCIE_BASE_
 sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIESS_LANE_TXD2_P" "PCIE_BASE_0:PCIESS_LANE_TXD2_P" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIESS_LANE_TXD3_N" "PCIE_BASE_0:PCIESS_LANE_TXD3_N" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIESS_LANE_TXD3_P" "PCIE_BASE_0:PCIESS_LANE_TXD3_P" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_BASE_0:AXI_CLK_125MHZ" "MSS:FIC_0_ACLK" "PCIE_AXI_0_0:ACLK" "PCIE_AXI_1_0:ACLK" "LSRAM_0:ACLK" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_BASE_0:APB_CLK_62_5MHZ" "MSS:FIC_3_PCLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_BASE_0:AXI_CLK_125MHZ" "MSS:FIC_0_ACLK" "MSS:FIC_1_ACLK" "PCIE_AXI_0_0:ACLK" "PCIE_AXI_1_0:ACLK" "LSRAM_0:ACLK" "LSRAM_1:ACLK" "COREAXI4DMACONTROLLER_0:CLOCK" "COREAXI4INTERCONNECT_0:ACLK"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_BASE_0:APB_CLK_62_5MHZ" "MSS:FIC_3_PCLK" "COREGPIO_C0:PCLK" "CORERESET_1:CLK"}
 sd_connect_pins -sd_name ${sd_name} -pin_names {"REF_CLK_PAD_N" "PCIE_BASE_0:REF_CLK_PAD_N" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"REF_CLK_PAD_P" "PCIE_BASE_0:REF_CLK_PAD_P" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"REFCLK" "MSS:REFCLK" }
@@ -267,6 +287,9 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"CAN_0_TXBUS_M2F" "MSS:CAN_0_TXB
 sd_connect_pins -sd_name ${sd_name} -pin_names {"CAN_1_RXBUS" "MSS:CAN_1_RXBUS" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"CAN_1_TX_EBL_N" "MSS:CAN_1_TX_EBL_N" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"CAN_1_TXBUS" "MSS:CAN_1_TXBUS" }
+sd_invert_pins -sd_name ${sd_name} -pin_names {"MSS:CAN_0_TX_EBL_M2F"} 
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAXI4DMACONTROLLER_0:INTERRUPT" "MSS:MSS_INT_F2M[2]" }
 sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {VSC_8662_CMODE3} -value {GND}
 sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {VSC_8662_CMODE4} -value {GND}
 sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {VSC_8662_CMODE5} -value {GND}
@@ -286,22 +309,59 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"DQS_N" "MSS:DQS_N" }
 
 # Add bus interface net connections
 sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:FIC_0_AXI4_MASTER" "PCIE_AXI_1_0:AXI4mmaster0" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_BASE_0:APBS" "MSS:FIC_3_APB_MASTER" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"COREABP3_C0:APB3mmaster" "MSS:FIC_3_APB_MASTER" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_AXI_0_0:AXI4mslave0" "MSS:FIC_0_AXI4_SLAVE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_AXI_0_0:AXI4mslave1" "LSRAM_1:AXI4_Slave" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_BASE_0:AXI_1_SLAVE" "PCIE_AXI_1_0:AXI4mslave0" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_AXI_0_0:AXI4mmaster0" "PCIE_BASE_0:AXI_1_MASTER" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_AXI_1_0:AXI4mslave1" "LSRAM_0:AXI4_Slave" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_AXI_1_0:AXI4mslave2" "COREAXI4DMACONTROLLER_0:AXI4SlaveCtrl_IF" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAXI4INTERCONNECT_0:AXI4mmaster0" "COREAXI4DMACONTROLLER_0:AXI4MasterDMA_IF" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAXI4INTERCONNECT_0:AXI4mslave0" "MSS:FIC_1_AXI4_SLAVE" }
+
+# Connect APB3 to PCIe base
+sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {PCIE_BASE_0:APBS} -pin_names {PCIE_BASE_0:PADDR} 
+sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {PCIE_BASE_0:APBS} -pin_names {PCIE_BASE_0:PSEL} 
+sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {PCIE_BASE_0:APBS} -pin_names {PCIE_BASE_0:PENABLE} 
+sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {PCIE_BASE_0:APBS} -pin_names {PCIE_BASE_0:PWRITE} 
+sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {PCIE_BASE_0:APBS} -pin_names {PCIE_BASE_0:PRDATA} 
+sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {PCIE_BASE_0:APBS} -pin_names {PCIE_BASE_0:PWDATA} 
+sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {PCIE_BASE_0:APBS} -pin_names {PCIE_BASE_0:PREADY} 
+sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {PCIE_BASE_0:APBS} -pin_names {PCIE_BASE_0:PSLVERR} 
+sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {COREABP3_C0:APBmslave3} -pin_names {COREABP3_C0:PADDRS} 
+sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {COREABP3_C0:APBmslave3} -pin_names {COREABP3_C0:PSELS3} 
+sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {COREABP3_C0:APBmslave3} -pin_names {COREABP3_C0:PENABLES} 
+sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {COREABP3_C0:APBmslave3} -pin_names {COREABP3_C0:PWRITES} 
+sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {COREABP3_C0:APBmslave3} -pin_names {COREABP3_C0:PRDATAS3} 
+sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {COREABP3_C0:APBmslave3} -pin_names {COREABP3_C0:PWDATAS} 
+sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {COREABP3_C0:APBmslave3} -pin_names {COREABP3_C0:PREADYS3} 
+sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {COREABP3_C0:APBmslave3} -pin_names {COREABP3_C0:PSLVERRS3} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_BASE_0:PRDATA" "COREABP3_C0:PRDATAS3"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_BASE_0:PREADY" "COREABP3_C0:PREADYS3"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_BASE_0:PSLVERR" "COREABP3_C0:PSLVERRS3"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {COREABP3_C0:PADDRS} -pin_slices {"[31:29]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {COREABP3_C0:PADDRS} -pin_slices {"[28:0]"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"COREABP3_C0:PADDRS[28:0]" "PCIE_BASE_0:PADDR"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"COREABP3_C0:PWDATAS" "PCIE_BASE_0:PWDATA"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"COREABP3_C0:PSELS3" "PCIE_BASE_0:PSEL"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"COREABP3_C0:PENABLES" "PCIE_BASE_0:PENABLE"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"COREABP3_C0:PWRITES" "PCIE_BASE_0:PWRITE"} 
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"COREABP3_C0:APBmslave2" "COREGPIO_C0:APB_bif" }
+
 
 # Fabric reset
-sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:MSS_RESET_N_M2F" "CORERESET_0:EXT_RST_N"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:MSS_RESET_N_M2F" "CORERESET_0:EXT_RST_N" "CORERESET_1:EXT_RST_N"} 
 sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_0:BANK_y_VDDI_STATUS} -value {VCC} 
 sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_0:BANK_x_VDDI_STATUS} -value {VCC} 
 sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_0:SS_BUSY} -value {GND} 
 sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_0:FF_US_RESTORE} -value {GND} 
-sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_MONITOR:FABRIC_POR_N" "CORERESET_0:FPGA_POR_N"} 
-sd_connect_pins -sd_name ${sd_name} -pin_names {\
-	"INIT_MONITOR:DEVICE_INIT_DONE" \
-	"CORERESET_0:INIT_DONE" }
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_1:BANK_y_VDDI_STATUS} -value {VCC} 
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_1:BANK_x_VDDI_STATUS} -value {VCC} 
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_1:SS_BUSY} -value {GND} 
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_1:FF_US_RESTORE} -value {GND} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_MONITOR:FABRIC_POR_N" "CORERESET_0:FPGA_POR_N" "CORERESET_1:FPGA_POR_N"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_MONITOR:DEVICE_INIT_DONE" "CORERESET_0:INIT_DONE" "CORERESET_1:INIT_DONE" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_BASE_0:AXI_CLK_125MHZ" "CORERESET_0:CLK"}
 
 #Invert pins