Constraints: add clock groups

Added async clock domain constraints for timing analysis
polarfire-soc · Oct 19, 2022 · 7a48fa3 · 7a48fa3
1 parent 8af0ec5
commit 7a48fa3
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Showing 4 changed files with 34 additions and 3 deletions.
diff --git a/MPFS_ICICLE_KIT_REFERENCE_DESIGN.tcl b/MPFS_ICICLE_KIT_REFERENCE_DESIGN.tcl
@@ -191,12 +191,19 @@ import_files \
     -io_pdc "${constraint_path}/ICICLE_I2C_LOOPBACK.pdc" \
     -io_pdc "${constraint_path}/ICICLE_SPI_LOOPBACK.pdc" \
     -io_pdc "${constraint_path}/ICICLE_RPi_MICRON_QSPI.pdc" \
-	-fp_pdc "${constraint_path}/NW_PLL.pdc"
+	-fp_pdc "${constraint_path}/NW_PLL.pdc" \
+	-sdc "${constraint_path}/fic_clocks.sdc"
 
 #
 # // Associate imported constraints with the design flow
 #
 
+organize_tool_files \
+	-tool {SYNTHESIZE} \
+	-file "${project_dir}/constraint/fic_clocks.sdc" \
+	-module {MPFS_ICICLE_KIT_BASE_DESIGN::work} \
+	-input_type {constraint} 
+
 if {[info exists MICRON_QSPI]} {
 	organize_tool_files \
 		-tool {PLACEROUTE} \
@@ -213,6 +220,7 @@ if {[info exists MICRON_QSPI]} {
 		-file "${project_dir}/constraint/io/ICICLE_MMUART2.pdc" \
 		-file "${project_dir}/constraint/io/ICICLE_RPi_MICRON_QSPI.pdc" \
 		-file "${project_dir}/constraint/fp/NW_PLL.pdc" \
+		-file "${project_dir}/constraint/fic_clocks.sdc" \
 		-module {MPFS_ICICLE_KIT_BASE_DESIGN::work} \
 		-input_type {constraint}
 } else {
@@ -231,15 +239,25 @@ if {[info exists MICRON_QSPI]} {
 		-file "${project_dir}/constraint/io/ICICLE_MMUART2.pdc" \
 		-file "${project_dir}/constraint/io/ICICLE_RPi.pdc" \
 		-file "${project_dir}/constraint/fp/NW_PLL.pdc" \
+		-file "${project_dir}/constraint/fic_clocks.sdc" \
 		-module {MPFS_ICICLE_KIT_BASE_DESIGN::work} \
 		-input_type {constraint}
 		}
+
+organize_tool_files \
+	-tool {VERIFYTIMING} \
+	-file "${project_dir}/constraint/fic_clocks.sdc" \
+	-module {MPFS_ICICLE_KIT_BASE_DESIGN::work} \
+	-input_type {constraint} 
+
+
 #
-# // Derive timing constraints
+# // Build hierarchy before progressing
 #
 
 build_design_hierarchy
-derive_constraints_sdc 
+
+
 
 #
 # // Apply additional design configurations
@@ -312,6 +330,13 @@ save_smartdesign -sd_name {MSS_WRAPPER}
 sd_reset_layout -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN}
 save_smartdesign -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN}
 
+#
+# // Derive timing constraints
+#
+
+build_design_hierarchy
+derive_constraints_sdc 
+
 #
 # // Run the design flow and add eNVM clients if required
 #

diff --git a/script_support/additional_configurations/I2C_LOOPBACK/I2C_LOOPBACK.tcl b/script_support/additional_configurations/I2C_LOOPBACK/I2C_LOOPBACK.tcl
@@ -48,5 +48,6 @@ organize_tool_files \
 	-file "${project_dir}/constraint/io/ICICLE_MMUART2.pdc" \
 	-file "${project_dir}/constraint/io/ICICLE_I2C_LOOPBACK.pdc" \
 	-file "${project_dir}/constraint/fp/NW_PLL.pdc" \
+	-file "${project_dir}/constraint/fic_clocks.sdc" \
 	-module {MPFS_ICICLE_KIT_BASE_DESIGN::work} \
 	-input_type {constraint} 
diff --git a/script_support/additional_configurations/SPI_LOOPBACK/SPI_LOOPBACK.tcl b/script_support/additional_configurations/SPI_LOOPBACK/SPI_LOOPBACK.tcl
@@ -53,5 +53,6 @@ organize_tool_files \
 	-file "${project_dir}/constraint/io/ICICLE_MMUART3.pdc" \
 	-file "${project_dir}/constraint/io/ICICLE_SPI_LOOPBACK.pdc" \
 	-file "${project_dir}/constraint/fp/NW_PLL.pdc" \
+	-file "${project_dir}/constraint/fic_clocks.sdc" \
 	-module {MPFS_ICICLE_KIT_BASE_DESIGN::work} \
 	-input_type {constraint} 
diff --git a/script_support/constraints/fic_clocks.sdc b/script_support/constraints/fic_clocks.sdc
@@ -0,0 +1,4 @@
+set_clock_groups -name {FIC0_clks} -asynchronous -group [ get_clocks { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT0 } ]
+set_clock_groups -name {FIC1_clks} -asynchronous -group [ get_clocks { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT1 } ]
+set_clock_groups -name {FIC2_clks} -asynchronous -group [ get_clocks { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT2 } ]
+set_clock_groups -name {FIC3_clks} -asynchronous -group [ get_clocks { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT3 } ]