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@ConchuOD ConchuOD released this 19 Oct 14:31
· 40 commits to master since this release
v2022.10
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ConchuOD Conor Dooley
GPG key ID: 78B43187A08262D2
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Icicle Kit Reference Design Release v2022.10

Note: this is an interim release to support Ubuntu Server on the Icicle Kit. This release updates the Icicle kit memory map, and is not compatible with releases prior to v2023.02.

For information on how to program a preinstalled Ubuntu Server Image to the Icicle Kit, please refer to the "Ubuntu Server Image" section of our documentation on how to update a PolarFire SoC development kit.

Changes since last release

  • Updated the addressing used for the AXI Address SHIM to offset addresses to 0x14_xxxx_xxxx instead of 0x10_xxxx_xxxx for PCIe transactions to use the non-cached DDR.
  • Updated the provided XML SEG register configuration to overlay DDR memory locations
    • The 32 bit cached, 32 bit non-cached, 38 bit cached and 38 bit non-cached DDR now point to the same physical addresses of DDR
    • This feature will be available from the Libero v2022.3 MSS configurator
  • Added a clock constraint to mark FIC clocks as asynchronous

Tested Libero version

This release has been tested with Libero SoC v2022.2

Pre-built programming files

The MPFS_ICICLE_BASE_DESIGN_2022_10.zip release asset contains a FlashPro Express programming file including both this Libero FPGA design and Hart Software Services release v2022.09 with the modified XML that is now provided.
This programming file can be used to program an Icicle Kit's FPGA and eNVM without having to run through the Libero FPGA flow or building the HSS.

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