Table of Contents

• aug-elfPlace
  • Hybrid Placement Framework
  • Target Architecture
• Publication(s)
• Developer(s)
• Cloning the Repository
• Build Instructions
  • To install Python dependency
  • To install with Docker
  • To Build
• Benchmarks
• Running aug-elfPlace
  • Integration with VPR
• Bug Report
• Copyright

aug-elfPlace

aug-elfPlace, built on the DREAMPlaceFPGA (commit 9b86a09) framework, is a wirelength-driven generalizable flat analytical FPGA placer that consists of a global placer and packer-legalizer. The main features of aug-elfPlace include:

• a generalized architecture modeling that reads in the architecture-specific details and legality constraints as an additional bookshelf input file (design.lc);
• employing the scalable auction algorithm to legalize a large number of digital signal processors (DSPs) and memory blocks in the design;
• using placeholder fillers to effectively handle memory logic array block (MLAB) instances in the design;
• employ a partial macro representation for carry chains;
• enhance the instance area update and packer-legalizer algorithms for look-up tables (LUTs) and flip-flops (FFs) to ensure legal placement for different architectures; and
• VPR-compatible flat output placement format.

aug-elfPlace can integrate with the open-source VPR CAD tool to further improve the quality of results through annealing as part of the hybrid placement framework. Please refer to our paper for detailed information.

Hybrid Placement Framework

The hybrid placement framework integrates a flat analytical placer such as aug-elfPlace with VPR's place and route tool using the VPR legalizer.

The VPR legalizer reads in a flat placement solution and constructs a cluster-level netlist for VPR's placer. The VPR legalizer also repairs any legality or mode-related errors in the clusters, thus allowing any external flat placer to integrate with VPR's place and route tool.

The placement solution from aug-elfPlace can be routed in VPR's router and validated to evaluate overall performance. In addition, VPR's annealing-based placer can further refine the aug-elfPlace solution to improve the overall quality of results.

Please refer to our paper for more details on the performance of aug-elfPlace as part of the hybrid placement framework on the Titan23 benchmarks benchmarks.

Target Architecture

aug-elfPlace can target simplified versions of the Ultrascale and Stratix-IV architectures and requires the locations of the fixed input-output (IO) and phase-locked loop (PLL) blocks to be provided as part of the input, similar to DREAMPlaceFPGA.

FPGA architectures consist of DSP blocks and different memory blocks - BRAM, M9K, and M144K, with Slice blocks that consist of LUT, FF, and adder instances.

Carry adder instances in the Ultrascale architecture are not shown in the Figure, as the benchmarks do not contain any.

Slice blocks are configurable logic blocks (CLBs) in Ultrascale architecture and logic array blocks (LABs) in Stratix-IV architecture. The architectures differ significantly in the configuration of the Slice blocks and the legality constraints for LUTs and FFs.

Simplified Ultrascale Architecture

• The ISPD'2016 benchmarks targeting a simplified AMD/Xilinx Ultrascale architecture. aug-elfPlace can be run on GPU and CPU for Ultrascale-like architectures.

Simplified Stratix-IV Architecture

• The Titan23 benchmarks targeting a simplified Intel/Altera Stratix-IV architecture. Due to large packer-legalizer runtime for the Stratix-IV-like architecture, aug-elfPlace is run on CPU.

Note: aug-elfPlace is not tested on the AMD/Xilinx Ultrascale+ or other architecture.

Publication(s)

• Rachel Selina Rajarathnam, Kate Thurmer, Vaughn Betz, Mahesh A. Iyer, and David Z. Pan, "Better Together: Combining Analytical and Annealing Methods for FPGA Placement," 34th International Conference on Field-Programmable Logic and Applications (FPL), 2024 (accepted).

Developer(s)

• Rachel Selina Rajarathnam, UTDA, ECE Department, The University of Texas at Austin

Cloning the Repository

External dependencies are the same as DREAMPlaceFPGA.

To pull git submodules in the root directory

git submodule init
git submodule update

Alternatively, pull all the submodules when cloning the repository.

git clone --recursive https://github.com/rachelselinar/aug-elfPlace.git

Build Instructions

To install Python dependency

There is an alternative way to install aug-elfPlace using Docker. If you want to use Docker, skip this step and go to Docker installation.

At the root directory:

pip install -r requirements.txt 

For example, if the repository was cloned in directory ~/Downloads, then the root directory is ~/Downloads/aug-elfPlace

You can also use a python virtual environment to install all the required packages to run aug-elfPlace

To install with Docker

You can use the Docker container to avoid building all the dependencies yourself.

1. Install Docker on Linux (Win and Mac are not tested).

2. To enable the GPU features, install NVIDIA-docker; otherwise, skip this step.

3. Get the docker image using one of the options Build the image locally.

   docker build . --file Dockerfile --tag <username>/dreamplacefpga:1.0
   

   Replace <username> with a username, for instance, 'utda_placer.'

4. Enter the bash environment of the container. Mount the repo and all the Designs into the Docker, which allows the Docker container to access and modify these files directly.

   To run on a Linux machine without GPU:

   docker run -it -v $(pwd):/aug-elfPlace <username>/dreamplacefpga:1.0 bash
   

   To run on a Linux machine with GPU: (Docker verified on NVIDIA GPUs with compute capability 6.1, 7.5, and 8.0)

   docker run --gpus 1 -it -v $(pwd):/aug-elfPlace <username>/dreamplacefpga:1.0 bash
   

   For example, to run on a Linux machine without GPU:

   docker run -it -v $(pwd):/aug-elfPlace utda_placer/dreamplacefpga:1.0 bash
   

5. Go to the aug-elfPlace directory in the Docker, which is the root directory of the project

   cd /aug-elfPlace
   

To Build

At the root directory,

mkdir build 
cd build 
cmake .. -DCMAKE_INSTALL_PREFIX=path_to_root_dir
make
make install

If you are using Docker, use the following at the root directory,

rm -rf build
mkdir build 
cd build 
cmake .. -DCMAKE_INSTALL_PREFIX=/aug-elfPlace -DPYTHON_EXECUTABLE=$(which python)
make
make install

Third-party submodules are automatically built except for Boost.

For example,

~/Downloads/aug-elfPlace: mkdir build; cd build

~/Downloads/aug-elfPlace/build: cmake . . -DCMAKE_INSTALL_PREFIX=~/Downloads/aug-elfPlace

~/Downloads/aug-elfPlace/build: make; make install

The directory ~/Downloads/aug-elfPlace/build is the install dir

When packages or parser code are changed, the contents of the build directory must be deleted for a clean build and proper operation.

rm -r build

For example,

~/Downloads/aug-elfPlace: rm -r build

For cmake options, refer to DREAMPlaceFPGA.

Benchmarks

aug-elfPlace only accepts inputs in the Bookshelf format and requires IO/PLL locations to be fixed.

• 12 designs for AMD/Xilinx Ultrascale Architecture in the updated bookshelf format with fixed IOs are provided from the ISPD'2016 contest.
• Titan23 designs based on the simplified Intel/Altera Stratix-IV Architecture, generated by VPR, are included in bookshelf format.

All the designs are in the benchmarks directory, and sample JSON configuration files are in the test directory. For the complete list of available options in the JSON file, please refer to paramsFPGA.json.

Running aug-elfPlace

Before running, ensure that all python dependent packages have been installed. Go to the root directory and run with the JSON configuration file.

python dreamplacefpga/Placer.py <benchmark>.json

Run from ~/Downloads/aug-elfPlace directory

For example:

python dreamplacefpga/Placer.py test/FPGA01.json

~/Downloads/aug-elfPlace: python dreamplacefpga/Placer.py test/FPGA01.json

If you are not using the GPU, change the gpu flag in the *.json file to 0.

Unit tests for some of the pytorch operators are provided. For instance, to run the unit test for hpwl, use the below command:

python unitest/ops/hpwl_unitest.py

Note: If your machine does not have an NVIDIA GPU, set the 'gpu' flag in the JSON configuration file to '0' to run on the CPU.

Integration with VPR

• Generate flat placement solution from aug-elfPlace in VPR compatible format as a .pl file:

<node_name>  x  y  s  z  <node_type>

Where 's' refers to subtile location, set to zero 's=0' for IO/PLL instances, whereas 'z=0' for DSP/memory/Slice instances.

• Use VPR legalizer to construct a cluster-level netlist for VPR after fixing any legality or mode-related failures. A '.net' clustered netlist and '.fix_clusters' placement file is generated from the VPR legalizer's output.

• To validate the placement solution without refinement in VPR, use the '.fix_clusters' file generated as '.place' input placement file to VPR. For details, refer to this comment. VPR router is run on the input placement followed by validation.

To refine the placement solution in VPR, list only IO/PLL instances in the '.fix_clusters' file and let the VPR placer refine the placement before routing and validation.

Note: Integration with VPR is verified only for the Titan23 benchmarks.

Bug Report

Please file an issue to report a bug.

Copyright

This software is released under a BSD 3-Clause "New" or "Revised" License. Please refer to LICENSE for details.