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147 Open 231 Closed
147 Open 231 Closed
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Issues list

google test throws sign conversion warnings
#1025 opened Dec 22, 2021 by rdaly525
InstanceVisitorPass does not allow passing in functors that have access to the class object itself.
#1017 opened Jul 26, 2021 by rdaly525
@rdaly525
Request for CoreIR compatible with Windows.
#1014 opened Jun 30, 2021 by Arka2BR
1
Compilation error on Apple M1 chip
#1009 opened May 9, 2021 by shi27feng
11
Add module longname C API c-api
#1003 opened Apr 13, 2021 by rsetaluri
@rsetaluri
add_dummy_inputs pass doesn't work with sliced signals
#995 opened Mar 24, 2021 by jack-melchert
@rdaly525
segfault when using prototype components.
#981 opened Feb 1, 2021 by mbstrange2
@rdaly525
44
Add Multiply optimization
#979 opened Jan 29, 2021 by rdaly525
@rdaly525
verilog ND-array generation should be packed arrays instead of unpacked arrays.
#974 opened Oct 27, 2020 by rdaly525
@leonardt @rdaly525
3
Why is IEEE compliance for CW floating point add/mul set to 0?
#972 opened Oct 26, 2020 by jack-melchert
2
Update JSON for Modern C++
#971 opened Oct 20, 2020 by rdaly525
1
@rdaly525
inline_single_instance pass should maintain instance name
#967 opened Oct 7, 2020 by rsetaluri
@rsetaluri @rdaly525
1
Having trouble at branch rm-ubuf-master
#959 opened Sep 3, 2020 by francisxu21
3
[RFC] Bit Pattern Support in coreir
#946 opened Aug 20, 2020 by leonardt
@leonardt @rsetaluri @rdaly525
6
Add a Custom Name for CoreIR Generator When Generate Verilog Feature Request
#941 opened Aug 17, 2020 by joyliu37
1
@rdaly525
14
Loading the same library twice creates two distinct namespace objects
#929 opened Aug 6, 2020 by rdaly525
@rdaly525
Floating Point Ops for Halide
#901 opened Jun 22, 2020 by rdaly525
@rdaly525
set printer pass as not an analysis pass
#888 opened May 2, 2020 by rdaly525
@rdaly525
Add metadata field for names that shouldn't be inlined in the verilog code generation
#884 opened May 1, 2020 by leonardt
coreir_wrap should be inlineable in verilog inlining
#883 opened May 1, 2020 by rdaly525
Proposal: Whitelisting/Blacklisting on passes
#882 opened Apr 28, 2020 by rdaly525
@rdaly525
inline_verilog cleanup
#867 opened Apr 12, 2020 by rdaly525
2 tasks
@leonardt @rsetaluri @rdaly525
add default optimzation flag to coreir binary
#862 opened Apr 1, 2020 by rdaly525
@rdaly525
Add pre-verilog pass to uniquify instance names to prevent aliasing with module port names.
#859 opened Mar 31, 2020 by rdaly525
RPATH for installed libraries
#851 opened Mar 11, 2020 by rswarbrick
@rdaly525
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