CoreIR Changes/Fixes #607
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CoreIR Changes/Fixes #607
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- Modified Module Declaration so that modules can now be generated with empty parameter lists (when generators require no parameters). Added ASSERT statements to ensure that other exceptions are still caught. - Modified RemoveBulkConnections pass so that a BitInOut type is recognized as a Bit Type.
Modified the Makefile of CoreIR with a Debug flag, in order to allow debugging with GDB.
Modified `verilog` pass of CoreIR so that the default generator parameter values are propagated to the Verilog writer.
Removed all unnecessary comments.
JKHHai
changed the title
leonardt
requested changes
Sep 14, 2018
| @@ -9,6 +9,7 @@ TARGET = dylib | |||
| prefix?=/usr/local | |||
| endif | |||
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| COREDEBUG = True | |||
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I don't think should be checked in, seems like a debugging setting for yourself? FYI you can pass this as a flag to make, e.g. make COREDEBUG=1, rather than setting it in the file explicitly
| @@ -27,7 +28,7 @@ CFLAGS = -Wall -fPIC | |||
| CXXFLAGS = -std=c++11 -Wall -fPIC -Werror | |||
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| ifdef COREDEBUG | |||
| CXXFLAGS += -O0 -g3 -D_GLIBCXX_DEBUG | |||
| CXXFLAGS += -O0 -g3 | |||
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What's the reason for this removal?
leonardt
reviewed
Sep 14, 2018
| // return false; | ||
| // } | ||
| // } | ||
| // } |
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Can you submit the code in the comments as a separate PR? Or you could include it in this PR, but it would be good to include a test case that shows what this fixes.
Merged
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Makes changes to the CoreIR library.
Main changes:
RemoveBulkConnections: Fixed a bug where inouts were not recognized as bit connectionsaddDefaultGenArgs: Fixed a bug where the default parameters were not being propagated to the Verilog writer.Module: Made changes to Module constructor, so that Modules can be generated with emptygenargs, for greater flexibility.