RgGen::VHDL is a RgGen plugin to generate RTL written in VHDL.
To install RgGen::VHDL, use the following command:
$ gem install rggen-vhdl
You need to tell RgGen to load RgGen::VHDL plugin. There are two ways.
$ rggen --plugin rggen-vhdl your_register_map.yml
$ export RGGEN_PLUGINS=${RGGEN_PLUGINS}:rggen-vhdl
$ rggen your_register_map.yml
Generated RTL modules are constructed by using common VHDL modules. You need to get them from the GitHub repository and set an envirnment variable to show their location.
- GitHub repository
- Environment variable
- RGGEN_VHDL_RTL_ROOT
$ git clone https://github.com/rggen/rggen-vhdl-rtl.git
$ export RGGEN_VHDL_RTL_ROOT=`pwd`/rggen-vhdl-rtl
Then, you can use generated RTL modules with your design. This is an example command.
$ simulator \
-f ${RGGEN_VHDL_RTL_ROOT}/compile.f
your_csr_0.vhd your_csr_1.vhd your_design.vhd
Feedbacks, bus reports, questions and etc. are welcome! You can post them bu using following ways:
Copyright © 2021-2024 Taichi Ishitani. RgGen::VHDL is licensed under the MIT License, see LICENSE for futher details.
Everyone interacting in the RgGen::VHDL project's codebases, issue trackers, chat rooms and mailing lists is expected to follow the code of conduct.