-
Notifications
You must be signed in to change notification settings - Fork 42
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Constraints for vector tuple types #43
Comments
It's safe to use
|
But how to pass certain fields of tuples as non-tuple vector registers? If Depositing/extracting vectors from tuple aggregate types seems to defeat the purpose of segment loads/stores, unless it's just massaging for the compiler and introduces no new instructions (moves). |
Yes, using vget/vset to depositing/extracting vectors from tuple types, compiler will try to allocate same register to prevent extra move instruction, if you saw a move instruction and you think it not necessary, you could report bug to llvm or GCC community since that might be potential performance regression issue. |
The tuple intrinsic type, since it's already a type outside of C/C++ proper, could have array indexing Even if array subscripting is not practical, some intrinsic like Porting code which used the old syntax would also be a lot easier, since you would only need to replace things like |
@leekillough honestly we've consider adding subscripting syntax for tuple type, I could imagining it would be useful and much simple for user - but unfortunately we are lack of engineering resource to implement that :( |
…code. However, it does not get correct results for complex BLIS routines which use segment loads (or call those that do). The intrinsic types check out and make sense, but it returns wrong answers. It's probably something really simple. For historical reference, see: riscv-non-isa/riscv-c-api-doc#43 flame#737 (comment) https://reviews.llvm.org/D152134 riscv-non-isa/rvv-intrinsic-doc#139 riscv-non-isa/rvv-intrinsic-doc#198 https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/auto-generated/intrinsic_funcs/02_vector_unit-stride_segment_load_store_instructions_zvlsseg.md https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/auto-generated/intrinsic_funcs/03_vector_stride_segment_load_store_instructions_zvlsseg.md https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/auto-generated/intrinsic_funcs/04_vector_indexed_segment_load_store_instructions_zvlsseg.md
Here's a preview of what not having such a feature would require doing, unless I'm missing something: Use the new tuple intrinsics to get rid of build errors in X280 BLIS |
How do we pass vector tuple types to/from extended asm templates? It seems that using the insertion/extraction intrinsics (with the first tuple element) might be unsafe.
@kito-cheng @leekillough
The text was updated successfully, but these errors were encountered: