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Improve segment load/store interface with tuple types #198
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@eopXD Maybe the return value with tuple type should directly return instead of using an argument to receive. It no need. void __riscv_vlseg2e8_v_i8mf8(vint8mf8x2_t *v_tuple, const int8_t *base, size_t vl); change to: vint8mf8x2_t __riscv_vlseg2e8_v_i8mf8(const int8_t *base, size_t vl); |
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I don't see the tuple types defined anywhere, although there are 300k LoC added in this PR and I may have skimmed over them. IIRC, they were removed a while back, perhaps here.
From an API perspective, I agree with other reviewers, suggesting that these loads return the tuple by value, to match other loads. My assumption is that these functions ("intrinsics") can be inlined by the compiler, so the ABI calling convention does not constrain register allocation in any way. (This assumption is supported by my experience with LLVM's implementation of these intrinsics.)
Thanks for the PR that we can have tuple type finally. Thanks. |
Should the name of vget/vset intrinsics be changed according to the tuple-type?
changed like this:
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Thanks for all the comment above. The latest force-push includes the following change:
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Cool, @eopXD, Thanks for making this happen! |
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LGTM, thanks @eopXD !
Hi, I found there is an issue with the naming of vset intrinsic: For normal LMUL > 1: I think the tuple vset naming should be changed into: |
I would like segment load/store have consistent naming rule for the return value part :
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Just notice it may generate some test functions like this (take vsoxseg7ei64.c as an example), not sure if there is something missing or not. void test_vsoxseg7ei64_v_f64m1(float64_t *base, vuint64m1_t bindex, vfloat64m1x7_t v_tuple, size_t vl) {
return __riscv_vsoxseg7ei64_v_f64m1(base, bindex, v_tuple, vl);
}
void test_vsoxseg7ei64_v_i8mf8(int8_t *base, vuint64m1_t bindex, vint8mf8x7_t v_tuple, size_t vl) {
return __riscv_vsoxseg7ei64_v_i8mf8(base, bindex, v_tuple, vl);
}
void test_vsoxseg7ei64_v_i8mf4(int8_t *base, vuint64m2_t bindex, vint8mf4x7_t v_tuple, size_t vl) {
return __riscv_vsoxseg7ei64_v_i8mf4(base, bindex, v_tuple, vl);
} |
The interface looks as intended. May you explain more, thank you. |
Sorry for misleading you, I mean the test function was declared as |
It is legal and should be fine, the store functions have a return type of |
Oh, I see, you would like to test the return type is void for the store intrinsic. That makes sense to me, thanks for the explanation. |
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Change:
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Add segment load/store intrinsics: riscv-non-isa/rvv-intrinsic-doc#198 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load): New function. (class vlseg): New class. (class vsseg): Ditto. (class vlsseg): Ditto. (class vssseg): Ditto. (class seg_indexed_load): Ditto. (class seg_indexed_store): Ditto. (class vlsegff): Ditto. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vlseg): Ditto. (vsseg): Ditto. (vlsseg): Ditto. (vssseg): Ditto. (vluxseg): Ditto. (vloxseg): Ditto. (vsuxseg): Ditto. (vsoxseg): Ditto. (vlsegff): Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct seg_loadstore_def): Ditto. (struct seg_indexed_loadstore_def): Ditto. (struct seg_fault_load_def): Ditto. (SHAPE): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (function_builder::append_nf): New function. * config/riscv/riscv-vector-builtins.def (vfloat32m1x2_t): Change ptr from double into float. (vfloat32m1x3_t): Ditto. (vfloat32m1x4_t): Ditto. (vfloat32m1x5_t): Ditto. (vfloat32m1x6_t): Ditto. (vfloat32m1x7_t): Ditto. (vfloat32m1x8_t): Ditto. (vfloat32m2x2_t): Ditto. (vfloat32m2x3_t): Ditto. (vfloat32m2x4_t): Ditto. (vfloat32m4x2_t): Ditto. * config/riscv/riscv-vector-builtins.h: Add segment intrinsics. * config/riscv/riscv-vsetvl.cc (fault_first_load_p): Adapt for segment ff load. * config/riscv/riscv.md: Add segment instructions. * config/riscv/vector-iterators.md: Support segment intrinsics. * config/riscv/vector.md (@pred_unit_strided_load<mode>): New pattern. (@pred_unit_strided_store<mode>): Ditto. (@pred_strided_load<mode>): Ditto. (@pred_strided_store<mode>): Ditto. (@pred_fault_load<mode>): Ditto. (@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto. (@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto. Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Just FYI that GCC upstream has supported the segment-related load/store already. Thanks @zhongjuzhe and @kito-cheng for making it happen. |
Signed-off-by: eop Chen <eop.chen@sifive.com>
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…code. However, it does not get correct results for complex BLIS routines which use segment loads (or call those that do). The intrinsic types check out and make sense, but it returns wrong answers. It's probably something really simple. For historical reference, see: riscv-non-isa/riscv-c-api-doc#43 flame#737 (comment) https://reviews.llvm.org/D152134 riscv-non-isa/rvv-intrinsic-doc#139 riscv-non-isa/rvv-intrinsic-doc#198 https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/auto-generated/intrinsic_funcs/02_vector_unit-stride_segment_load_store_instructions_zvlsseg.md https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/auto-generated/intrinsic_funcs/03_vector_stride_segment_load_store_instructions_zvlsseg.md https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/auto-generated/intrinsic_funcs/04_vector_indexed_segment_load_store_instructions_zvlsseg.md
Add segment load/store intrinsics: riscv-non-isa/rvv-intrinsic-doc#198 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load): New function. (class vlseg): New class. (class vsseg): Ditto. (class vlsseg): Ditto. (class vssseg): Ditto. (class seg_indexed_load): Ditto. (class seg_indexed_store): Ditto. (class vlsegff): Ditto. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vlseg): Ditto. (vsseg): Ditto. (vlsseg): Ditto. (vssseg): Ditto. (vluxseg): Ditto. (vloxseg): Ditto. (vsuxseg): Ditto. (vsoxseg): Ditto. (vlsegff): Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct seg_loadstore_def): Ditto. (struct seg_indexed_loadstore_def): Ditto. (struct seg_fault_load_def): Ditto. (SHAPE): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (function_builder::append_nf): New function. * config/riscv/riscv-vector-builtins.def (vfloat32m1x2_t): Change ptr from double into float. (vfloat32m1x3_t): Ditto. (vfloat32m1x4_t): Ditto. (vfloat32m1x5_t): Ditto. (vfloat32m1x6_t): Ditto. (vfloat32m1x7_t): Ditto. (vfloat32m1x8_t): Ditto. (vfloat32m2x2_t): Ditto. (vfloat32m2x3_t): Ditto. (vfloat32m2x4_t): Ditto. (vfloat32m4x2_t): Ditto. * config/riscv/riscv-vector-builtins.h: Add segment intrinsics. * config/riscv/riscv-vsetvl.cc (fault_first_load_p): Adapt for segment ff load. * config/riscv/riscv.md: Add segment instructions. * config/riscv/vector-iterators.md: Support segment intrinsics. * config/riscv/vector.md (@pred_unit_strided_load<mode>): New pattern. (@pred_unit_strided_store<mode>): Ditto. (@pred_strided_load<mode>): Ditto. (@pred_strided_store<mode>): Ditto. (@pred_fault_load<mode>): Ditto. (@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto. (@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto. Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Add segment load/store intrinsics: riscv-non-isa/rvv-intrinsic-doc#198 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load): New function. (class vlseg): New class. (class vsseg): Ditto. (class vlsseg): Ditto. (class vssseg): Ditto. (class seg_indexed_load): Ditto. (class seg_indexed_store): Ditto. (class vlsegff): Ditto. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vlseg): Ditto. (vsseg): Ditto. (vlsseg): Ditto. (vssseg): Ditto. (vluxseg): Ditto. (vloxseg): Ditto. (vsuxseg): Ditto. (vsoxseg): Ditto. (vlsegff): Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct seg_loadstore_def): Ditto. (struct seg_indexed_loadstore_def): Ditto. (struct seg_fault_load_def): Ditto. (SHAPE): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (function_builder::append_nf): New function. * config/riscv/riscv-vector-builtins.def (vfloat32m1x2_t): Change ptr from double into float. (vfloat32m1x3_t): Ditto. (vfloat32m1x4_t): Ditto. (vfloat32m1x5_t): Ditto. (vfloat32m1x6_t): Ditto. (vfloat32m1x7_t): Ditto. (vfloat32m1x8_t): Ditto. (vfloat32m2x2_t): Ditto. (vfloat32m2x3_t): Ditto. (vfloat32m2x4_t): Ditto. (vfloat32m4x2_t): Ditto. * config/riscv/riscv-vector-builtins.h: Add segment intrinsics. * config/riscv/riscv-vsetvl.cc (fault_first_load_p): Adapt for segment ff load. * config/riscv/riscv.md: Add segment instructions. * config/riscv/vector-iterators.md: Support segment intrinsics. * config/riscv/vector.md (@pred_unit_strided_load<mode>): New pattern. (@pred_unit_strided_store<mode>): Ditto. (@pred_strided_load<mode>): Ditto. (@pred_strided_store<mode>): Ditto. (@pred_fault_load<mode>): Ditto. (@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto. (@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto. Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Add segment load/store intrinsics: riscv-non-isa/rvv-intrinsic-doc#198 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load): New function. (class vlseg): New class. (class vsseg): Ditto. (class vlsseg): Ditto. (class vssseg): Ditto. (class seg_indexed_load): Ditto. (class seg_indexed_store): Ditto. (class vlsegff): Ditto. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vlseg): Ditto. (vsseg): Ditto. (vlsseg): Ditto. (vssseg): Ditto. (vluxseg): Ditto. (vloxseg): Ditto. (vsuxseg): Ditto. (vsoxseg): Ditto. (vlsegff): Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct seg_loadstore_def): Ditto. (struct seg_indexed_loadstore_def): Ditto. (struct seg_fault_load_def): Ditto. (SHAPE): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (function_builder::append_nf): New function. * config/riscv/riscv-vector-builtins.def (vfloat32m1x2_t): Change ptr from double into float. (vfloat32m1x3_t): Ditto. (vfloat32m1x4_t): Ditto. (vfloat32m1x5_t): Ditto. (vfloat32m1x6_t): Ditto. (vfloat32m1x7_t): Ditto. (vfloat32m1x8_t): Ditto. (vfloat32m2x2_t): Ditto. (vfloat32m2x3_t): Ditto. (vfloat32m2x4_t): Ditto. (vfloat32m4x2_t): Ditto. * config/riscv/riscv-vector-builtins.h: Add segment intrinsics. * config/riscv/riscv-vsetvl.cc (fault_first_load_p): Adapt for segment ff load. * config/riscv/riscv.md: Add segment instructions. * config/riscv/vector-iterators.md: Support segment intrinsics. * config/riscv/vector.md (@pred_unit_strided_load<mode>): New pattern. (@pred_unit_strided_store<mode>): Ditto. (@pred_strided_load<mode>): Ditto. (@pred_strided_store<mode>): Ditto. (@pred_fault_load<mode>): Ditto. (@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto. (@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto. Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Add segment load/store intrinsics: riscv-non-isa/rvv-intrinsic-doc#198 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load): New function. (class vlseg): New class. (class vsseg): Ditto. (class vlsseg): Ditto. (class vssseg): Ditto. (class seg_indexed_load): Ditto. (class seg_indexed_store): Ditto. (class vlsegff): Ditto. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vlseg): Ditto. (vsseg): Ditto. (vlsseg): Ditto. (vssseg): Ditto. (vluxseg): Ditto. (vloxseg): Ditto. (vsuxseg): Ditto. (vsoxseg): Ditto. (vlsegff): Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct seg_loadstore_def): Ditto. (struct seg_indexed_loadstore_def): Ditto. (struct seg_fault_load_def): Ditto. (SHAPE): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (function_builder::append_nf): New function. * config/riscv/riscv-vector-builtins.def (vfloat32m1x2_t): Change ptr from double into float. (vfloat32m1x3_t): Ditto. (vfloat32m1x4_t): Ditto. (vfloat32m1x5_t): Ditto. (vfloat32m1x6_t): Ditto. (vfloat32m1x7_t): Ditto. (vfloat32m1x8_t): Ditto. (vfloat32m2x2_t): Ditto. (vfloat32m2x3_t): Ditto. (vfloat32m2x4_t): Ditto. (vfloat32m4x2_t): Ditto. * config/riscv/riscv-vector-builtins.h: Add segment intrinsics. * config/riscv/riscv-vsetvl.cc (fault_first_load_p): Adapt for segment ff load. * config/riscv/riscv.md: Add segment instructions. * config/riscv/vector-iterators.md: Support segment intrinsics. * config/riscv/vector.md (@pred_unit_strided_load<mode>): New pattern. (@pred_unit_strided_store<mode>): Ditto. (@pred_strided_load<mode>): Ditto. (@pred_strided_store<mode>): Ditto. (@pred_fault_load<mode>): Ditto. (@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto. (@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto. Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Add segment load/store intrinsics: riscv-non-isa/rvv-intrinsic-doc#198 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load): New function. (class vlseg): New class. (class vsseg): Ditto. (class vlsseg): Ditto. (class vssseg): Ditto. (class seg_indexed_load): Ditto. (class seg_indexed_store): Ditto. (class vlsegff): Ditto. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vlseg): Ditto. (vsseg): Ditto. (vlsseg): Ditto. (vssseg): Ditto. (vluxseg): Ditto. (vloxseg): Ditto. (vsuxseg): Ditto. (vsoxseg): Ditto. (vlsegff): Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct seg_loadstore_def): Ditto. (struct seg_indexed_loadstore_def): Ditto. (struct seg_fault_load_def): Ditto. (SHAPE): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (function_builder::append_nf): New function. * config/riscv/riscv-vector-builtins.def (vfloat32m1x2_t): Change ptr from double into float. (vfloat32m1x3_t): Ditto. (vfloat32m1x4_t): Ditto. (vfloat32m1x5_t): Ditto. (vfloat32m1x6_t): Ditto. (vfloat32m1x7_t): Ditto. (vfloat32m1x8_t): Ditto. (vfloat32m2x2_t): Ditto. (vfloat32m2x3_t): Ditto. (vfloat32m2x4_t): Ditto. (vfloat32m4x2_t): Ditto. * config/riscv/riscv-vector-builtins.h: Add segment intrinsics. * config/riscv/riscv-vsetvl.cc (fault_first_load_p): Adapt for segment ff load. * config/riscv/riscv.md: Add segment instructions. * config/riscv/vector-iterators.md: Support segment intrinsics. * config/riscv/vector.md (@pred_unit_strided_load<mode>): New pattern. (@pred_unit_strided_store<mode>): Ditto. (@pred_strided_load<mode>): Ditto. (@pred_strided_store<mode>): Ditto. (@pred_fault_load<mode>): Ditto. (@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto. (@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto. Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Add segment load/store intrinsics: riscv-non-isa/rvv-intrinsic-doc#198 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load): New function. (class vlseg): New class. (class vsseg): Ditto. (class vlsseg): Ditto. (class vssseg): Ditto. (class seg_indexed_load): Ditto. (class seg_indexed_store): Ditto. (class vlsegff): Ditto. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vlseg): Ditto. (vsseg): Ditto. (vlsseg): Ditto. (vssseg): Ditto. (vluxseg): Ditto. (vloxseg): Ditto. (vsuxseg): Ditto. (vsoxseg): Ditto. (vlsegff): Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct seg_loadstore_def): Ditto. (struct seg_indexed_loadstore_def): Ditto. (struct seg_fault_load_def): Ditto. (SHAPE): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (function_builder::append_nf): New function. * config/riscv/riscv-vector-builtins.def (vfloat32m1x2_t): Change ptr from double into float. (vfloat32m1x3_t): Ditto. (vfloat32m1x4_t): Ditto. (vfloat32m1x5_t): Ditto. (vfloat32m1x6_t): Ditto. (vfloat32m1x7_t): Ditto. (vfloat32m1x8_t): Ditto. (vfloat32m2x2_t): Ditto. (vfloat32m2x3_t): Ditto. (vfloat32m2x4_t): Ditto. (vfloat32m4x2_t): Ditto. * config/riscv/riscv-vector-builtins.h: Add segment intrinsics. * config/riscv/riscv-vsetvl.cc (fault_first_load_p): Adapt for segment ff load. * config/riscv/riscv.md: Add segment instructions. * config/riscv/vector-iterators.md: Support segment intrinsics. * config/riscv/vector.md (@pred_unit_strided_load<mode>): New pattern. (@pred_unit_strided_store<mode>): Ditto. (@pred_strided_load<mode>): Ditto. (@pred_strided_store<mode>): Ditto. (@pred_fault_load<mode>): Ditto. (@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto. (@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto. Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Add segment load/store intrinsics: riscv-non-isa/rvv-intrinsic-doc#198 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load): New function. (class vlseg): New class. (class vsseg): Ditto. (class vlsseg): Ditto. (class vssseg): Ditto. (class seg_indexed_load): Ditto. (class seg_indexed_store): Ditto. (class vlsegff): Ditto. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vlseg): Ditto. (vsseg): Ditto. (vlsseg): Ditto. (vssseg): Ditto. (vluxseg): Ditto. (vloxseg): Ditto. (vsuxseg): Ditto. (vsoxseg): Ditto. (vlsegff): Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct seg_loadstore_def): Ditto. (struct seg_indexed_loadstore_def): Ditto. (struct seg_fault_load_def): Ditto. (SHAPE): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (function_builder::append_nf): New function. * config/riscv/riscv-vector-builtins.def (vfloat32m1x2_t): Change ptr from double into float. (vfloat32m1x3_t): Ditto. (vfloat32m1x4_t): Ditto. (vfloat32m1x5_t): Ditto. (vfloat32m1x6_t): Ditto. (vfloat32m1x7_t): Ditto. (vfloat32m1x8_t): Ditto. (vfloat32m2x2_t): Ditto. (vfloat32m2x3_t): Ditto. (vfloat32m2x4_t): Ditto. (vfloat32m4x2_t): Ditto. * config/riscv/riscv-vector-builtins.h: Add segment intrinsics. * config/riscv/riscv-vsetvl.cc (fault_first_load_p): Adapt for segment ff load. * config/riscv/riscv.md: Add segment instructions. * config/riscv/vector-iterators.md: Support segment intrinsics. * config/riscv/vector.md (@pred_unit_strided_load<mode>): New pattern. (@pred_unit_strided_store<mode>): Ditto. (@pred_strided_load<mode>): Ditto. (@pred_strided_store<mode>): Ditto. (@pred_fault_load<mode>): Ditto. (@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto. (@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto. Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Add segment load/store intrinsics: riscv-non-isa/rvv-intrinsic-doc#198 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load): New function. (class vlseg): New class. (class vsseg): Ditto. (class vlsseg): Ditto. (class vssseg): Ditto. (class seg_indexed_load): Ditto. (class seg_indexed_store): Ditto. (class vlsegff): Ditto. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vlseg): Ditto. (vsseg): Ditto. (vlsseg): Ditto. (vssseg): Ditto. (vluxseg): Ditto. (vloxseg): Ditto. (vsuxseg): Ditto. (vsoxseg): Ditto. (vlsegff): Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct seg_loadstore_def): Ditto. (struct seg_indexed_loadstore_def): Ditto. (struct seg_fault_load_def): Ditto. (SHAPE): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (function_builder::append_nf): New function. * config/riscv/riscv-vector-builtins.def (vfloat32m1x2_t): Change ptr from double into float. (vfloat32m1x3_t): Ditto. (vfloat32m1x4_t): Ditto. (vfloat32m1x5_t): Ditto. (vfloat32m1x6_t): Ditto. (vfloat32m1x7_t): Ditto. (vfloat32m1x8_t): Ditto. (vfloat32m2x2_t): Ditto. (vfloat32m2x3_t): Ditto. (vfloat32m2x4_t): Ditto. (vfloat32m4x2_t): Ditto. * config/riscv/riscv-vector-builtins.h: Add segment intrinsics. * config/riscv/riscv-vsetvl.cc (fault_first_load_p): Adapt for segment ff load. * config/riscv/riscv.md: Add segment instructions. * config/riscv/vector-iterators.md: Support segment intrinsics. * config/riscv/vector.md (@pred_unit_strided_load<mode>): New pattern. (@pred_unit_strided_store<mode>): Ditto. (@pred_strided_load<mode>): Ditto. (@pred_strided_store<mode>): Ditto. (@pred_fault_load<mode>): Ditto. (@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto. (@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto. Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Add segment load/store intrinsics: riscv-non-isa/rvv-intrinsic-doc#198 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load): New function. (class vlseg): New class. (class vsseg): Ditto. (class vlsseg): Ditto. (class vssseg): Ditto. (class seg_indexed_load): Ditto. (class seg_indexed_store): Ditto. (class vlsegff): Ditto. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vlseg): Ditto. (vsseg): Ditto. (vlsseg): Ditto. (vssseg): Ditto. (vluxseg): Ditto. (vloxseg): Ditto. (vsuxseg): Ditto. (vsoxseg): Ditto. (vlsegff): Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct seg_loadstore_def): Ditto. (struct seg_indexed_loadstore_def): Ditto. (struct seg_fault_load_def): Ditto. (SHAPE): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (function_builder::append_nf): New function. * config/riscv/riscv-vector-builtins.def (vfloat32m1x2_t): Change ptr from double into float. (vfloat32m1x3_t): Ditto. (vfloat32m1x4_t): Ditto. (vfloat32m1x5_t): Ditto. (vfloat32m1x6_t): Ditto. (vfloat32m1x7_t): Ditto. (vfloat32m1x8_t): Ditto. (vfloat32m2x2_t): Ditto. (vfloat32m2x3_t): Ditto. (vfloat32m2x4_t): Ditto. (vfloat32m4x2_t): Ditto. * config/riscv/riscv-vector-builtins.h: Add segment intrinsics. * config/riscv/riscv-vsetvl.cc (fault_first_load_p): Adapt for segment ff load. * config/riscv/riscv.md: Add segment instructions. * config/riscv/vector-iterators.md: Support segment intrinsics. * config/riscv/vector.md (@pred_unit_strided_load<mode>): New pattern. (@pred_unit_strided_store<mode>): Ditto. (@pred_strided_load<mode>): Ditto. (@pred_strided_store<mode>): Ditto. (@pred_fault_load<mode>): Ditto. (@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto. (@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto. Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Add segment load/store intrinsics: riscv-non-isa/rvv-intrinsic-doc#198 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load): New function. (class vlseg): New class. (class vsseg): Ditto. (class vlsseg): Ditto. (class vssseg): Ditto. (class seg_indexed_load): Ditto. (class seg_indexed_store): Ditto. (class vlsegff): Ditto. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vlseg): Ditto. (vsseg): Ditto. (vlsseg): Ditto. (vssseg): Ditto. (vluxseg): Ditto. (vloxseg): Ditto. (vsuxseg): Ditto. (vsoxseg): Ditto. (vlsegff): Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct seg_loadstore_def): Ditto. (struct seg_indexed_loadstore_def): Ditto. (struct seg_fault_load_def): Ditto. (SHAPE): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (function_builder::append_nf): New function. * config/riscv/riscv-vector-builtins.def (vfloat32m1x2_t): Change ptr from double into float. (vfloat32m1x3_t): Ditto. (vfloat32m1x4_t): Ditto. (vfloat32m1x5_t): Ditto. (vfloat32m1x6_t): Ditto. (vfloat32m1x7_t): Ditto. (vfloat32m1x8_t): Ditto. (vfloat32m2x2_t): Ditto. (vfloat32m2x3_t): Ditto. (vfloat32m2x4_t): Ditto. (vfloat32m4x2_t): Ditto. * config/riscv/riscv-vector-builtins.h: Add segment intrinsics. * config/riscv/riscv-vsetvl.cc (fault_first_load_p): Adapt for segment ff load. * config/riscv/riscv.md: Add segment instructions. * config/riscv/vector-iterators.md: Support segment intrinsics. * config/riscv/vector.md (@pred_unit_strided_load<mode>): New pattern. (@pred_unit_strided_store<mode>): Ditto. (@pred_strided_load<mode>): Ditto. (@pred_strided_store<mode>): Ditto. (@pred_fault_load<mode>): Ditto. (@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto. (@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto. Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Add segment load/store intrinsics: riscv-non-isa/rvv-intrinsic-doc#198 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load): New function. (class vlseg): New class. (class vsseg): Ditto. (class vlsseg): Ditto. (class vssseg): Ditto. (class seg_indexed_load): Ditto. (class seg_indexed_store): Ditto. (class vlsegff): Ditto. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vlseg): Ditto. (vsseg): Ditto. (vlsseg): Ditto. (vssseg): Ditto. (vluxseg): Ditto. (vloxseg): Ditto. (vsuxseg): Ditto. (vsoxseg): Ditto. (vlsegff): Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct seg_loadstore_def): Ditto. (struct seg_indexed_loadstore_def): Ditto. (struct seg_fault_load_def): Ditto. (SHAPE): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (function_builder::append_nf): New function. * config/riscv/riscv-vector-builtins.def (vfloat32m1x2_t): Change ptr from double into float. (vfloat32m1x3_t): Ditto. (vfloat32m1x4_t): Ditto. (vfloat32m1x5_t): Ditto. (vfloat32m1x6_t): Ditto. (vfloat32m1x7_t): Ditto. (vfloat32m1x8_t): Ditto. (vfloat32m2x2_t): Ditto. (vfloat32m2x3_t): Ditto. (vfloat32m2x4_t): Ditto. (vfloat32m4x2_t): Ditto. * config/riscv/riscv-vector-builtins.h: Add segment intrinsics. * config/riscv/riscv-vsetvl.cc (fault_first_load_p): Adapt for segment ff load. * config/riscv/riscv.md: Add segment instructions. * config/riscv/vector-iterators.md: Support segment intrinsics. * config/riscv/vector.md (@pred_unit_strided_load<mode>): New pattern. (@pred_unit_strided_store<mode>): Ditto. (@pred_strided_load<mode>): Ditto. (@pred_strided_store<mode>): Ditto. (@pred_fault_load<mode>): Ditto. (@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto. (@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto. Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Add segment load/store intrinsics: riscv-non-isa/rvv-intrinsic-doc#198 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load): New function. (class vlseg): New class. (class vsseg): Ditto. (class vlsseg): Ditto. (class vssseg): Ditto. (class seg_indexed_load): Ditto. (class seg_indexed_store): Ditto. (class vlsegff): Ditto. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vlseg): Ditto. (vsseg): Ditto. (vlsseg): Ditto. (vssseg): Ditto. (vluxseg): Ditto. (vloxseg): Ditto. (vsuxseg): Ditto. (vsoxseg): Ditto. (vlsegff): Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct seg_loadstore_def): Ditto. (struct seg_indexed_loadstore_def): Ditto. (struct seg_fault_load_def): Ditto. (SHAPE): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (function_builder::append_nf): New function. * config/riscv/riscv-vector-builtins.def (vfloat32m1x2_t): Change ptr from double into float. (vfloat32m1x3_t): Ditto. (vfloat32m1x4_t): Ditto. (vfloat32m1x5_t): Ditto. (vfloat32m1x6_t): Ditto. (vfloat32m1x7_t): Ditto. (vfloat32m1x8_t): Ditto. (vfloat32m2x2_t): Ditto. (vfloat32m2x3_t): Ditto. (vfloat32m2x4_t): Ditto. (vfloat32m4x2_t): Ditto. * config/riscv/riscv-vector-builtins.h: Add segment intrinsics. * config/riscv/riscv-vsetvl.cc (fault_first_load_p): Adapt for segment ff load. * config/riscv/riscv.md: Add segment instructions. * config/riscv/vector-iterators.md: Support segment intrinsics. * config/riscv/vector.md (@pred_unit_strided_load<mode>): New pattern. (@pred_unit_strided_store<mode>): Ditto. (@pred_strided_load<mode>): Ditto. (@pred_strided_store<mode>): Ditto. (@pred_fault_load<mode>): Ditto. (@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto. (@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto. Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Add segment load/store intrinsics: riscv-non-isa/rvv-intrinsic-doc#198 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load): New function. (class vlseg): New class. (class vsseg): Ditto. (class vlsseg): Ditto. (class vssseg): Ditto. (class seg_indexed_load): Ditto. (class seg_indexed_store): Ditto. (class vlsegff): Ditto. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vlseg): Ditto. (vsseg): Ditto. (vlsseg): Ditto. (vssseg): Ditto. (vluxseg): Ditto. (vloxseg): Ditto. (vsuxseg): Ditto. (vsoxseg): Ditto. (vlsegff): Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct seg_loadstore_def): Ditto. (struct seg_indexed_loadstore_def): Ditto. (struct seg_fault_load_def): Ditto. (SHAPE): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (function_builder::append_nf): New function. * config/riscv/riscv-vector-builtins.def (vfloat32m1x2_t): Change ptr from double into float. (vfloat32m1x3_t): Ditto. (vfloat32m1x4_t): Ditto. (vfloat32m1x5_t): Ditto. (vfloat32m1x6_t): Ditto. (vfloat32m1x7_t): Ditto. (vfloat32m1x8_t): Ditto. (vfloat32m2x2_t): Ditto. (vfloat32m2x3_t): Ditto. (vfloat32m2x4_t): Ditto. (vfloat32m4x2_t): Ditto. * config/riscv/riscv-vector-builtins.h: Add segment intrinsics. * config/riscv/riscv-vsetvl.cc (fault_first_load_p): Adapt for segment ff load. * config/riscv/riscv.md: Add segment instructions. * config/riscv/vector-iterators.md: Support segment intrinsics. * config/riscv/vector.md (@pred_unit_strided_load<mode>): New pattern. (@pred_unit_strided_store<mode>): Ditto. (@pred_strided_load<mode>): Ditto. (@pred_strided_store<mode>): Ditto. (@pred_fault_load<mode>): Ditto. (@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto. (@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto. Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Add segment load/store intrinsics: riscv-non-isa/rvv-intrinsic-doc#198 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load): New function. (class vlseg): New class. (class vsseg): Ditto. (class vlsseg): Ditto. (class vssseg): Ditto. (class seg_indexed_load): Ditto. (class seg_indexed_store): Ditto. (class vlsegff): Ditto. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vlseg): Ditto. (vsseg): Ditto. (vlsseg): Ditto. (vssseg): Ditto. (vluxseg): Ditto. (vloxseg): Ditto. (vsuxseg): Ditto. (vsoxseg): Ditto. (vlsegff): Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct seg_loadstore_def): Ditto. (struct seg_indexed_loadstore_def): Ditto. (struct seg_fault_load_def): Ditto. (SHAPE): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (function_builder::append_nf): New function. * config/riscv/riscv-vector-builtins.def (vfloat32m1x2_t): Change ptr from double into float. (vfloat32m1x3_t): Ditto. (vfloat32m1x4_t): Ditto. (vfloat32m1x5_t): Ditto. (vfloat32m1x6_t): Ditto. (vfloat32m1x7_t): Ditto. (vfloat32m1x8_t): Ditto. (vfloat32m2x2_t): Ditto. (vfloat32m2x3_t): Ditto. (vfloat32m2x4_t): Ditto. (vfloat32m4x2_t): Ditto. * config/riscv/riscv-vector-builtins.h: Add segment intrinsics. * config/riscv/riscv-vsetvl.cc (fault_first_load_p): Adapt for segment ff load. * config/riscv/riscv.md: Add segment instructions. * config/riscv/vector-iterators.md: Support segment intrinsics. * config/riscv/vector.md (@pred_unit_strided_load<mode>): New pattern. (@pred_unit_strided_store<mode>): Ditto. (@pred_strided_load<mode>): Ditto. (@pred_strided_store<mode>): Ditto. (@pred_fault_load<mode>): Ditto. (@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto. (@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto. Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Add segment load/store intrinsics: riscv-non-isa/rvv-intrinsic-doc#198 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load): New function. (class vlseg): New class. (class vsseg): Ditto. (class vlsseg): Ditto. (class vssseg): Ditto. (class seg_indexed_load): Ditto. (class seg_indexed_store): Ditto. (class vlsegff): Ditto. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vlseg): Ditto. (vsseg): Ditto. (vlsseg): Ditto. (vssseg): Ditto. (vluxseg): Ditto. (vloxseg): Ditto. (vsuxseg): Ditto. (vsoxseg): Ditto. (vlsegff): Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct seg_loadstore_def): Ditto. (struct seg_indexed_loadstore_def): Ditto. (struct seg_fault_load_def): Ditto. (SHAPE): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (function_builder::append_nf): New function. * config/riscv/riscv-vector-builtins.def (vfloat32m1x2_t): Change ptr from double into float. (vfloat32m1x3_t): Ditto. (vfloat32m1x4_t): Ditto. (vfloat32m1x5_t): Ditto. (vfloat32m1x6_t): Ditto. (vfloat32m1x7_t): Ditto. (vfloat32m1x8_t): Ditto. (vfloat32m2x2_t): Ditto. (vfloat32m2x3_t): Ditto. (vfloat32m2x4_t): Ditto. (vfloat32m4x2_t): Ditto. * config/riscv/riscv-vector-builtins.h: Add segment intrinsics. * config/riscv/riscv-vsetvl.cc (fault_first_load_p): Adapt for segment ff load. * config/riscv/riscv.md: Add segment instructions. * config/riscv/vector-iterators.md: Support segment intrinsics. * config/riscv/vector.md (@pred_unit_strided_load<mode>): New pattern. (@pred_unit_strided_store<mode>): Ditto. (@pred_strided_load<mode>): Ditto. (@pred_strided_store<mode>): Ditto. (@pred_fault_load<mode>): Ditto. (@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto. (@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto. Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Add segment load/store intrinsics: riscv-non-isa/rvv-intrinsic-doc#198 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load): New function. (class vlseg): New class. (class vsseg): Ditto. (class vlsseg): Ditto. (class vssseg): Ditto. (class seg_indexed_load): Ditto. (class seg_indexed_store): Ditto. (class vlsegff): Ditto. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vlseg): Ditto. (vsseg): Ditto. (vlsseg): Ditto. (vssseg): Ditto. (vluxseg): Ditto. (vloxseg): Ditto. (vsuxseg): Ditto. (vsoxseg): Ditto. (vlsegff): Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct seg_loadstore_def): Ditto. (struct seg_indexed_loadstore_def): Ditto. (struct seg_fault_load_def): Ditto. (SHAPE): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (function_builder::append_nf): New function. * config/riscv/riscv-vector-builtins.def (vfloat32m1x2_t): Change ptr from double into float. (vfloat32m1x3_t): Ditto. (vfloat32m1x4_t): Ditto. (vfloat32m1x5_t): Ditto. (vfloat32m1x6_t): Ditto. (vfloat32m1x7_t): Ditto. (vfloat32m1x8_t): Ditto. (vfloat32m2x2_t): Ditto. (vfloat32m2x3_t): Ditto. (vfloat32m2x4_t): Ditto. (vfloat32m4x2_t): Ditto. * config/riscv/riscv-vector-builtins.h: Add segment intrinsics. * config/riscv/riscv-vsetvl.cc (fault_first_load_p): Adapt for segment ff load. * config/riscv/riscv.md: Add segment instructions. * config/riscv/vector-iterators.md: Support segment intrinsics. * config/riscv/vector.md (@pred_unit_strided_load<mode>): New pattern. (@pred_unit_strided_store<mode>): Ditto. (@pred_strided_load<mode>): Ditto. (@pred_strided_store<mode>): Ditto. (@pred_fault_load<mode>): Ditto. (@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto. (@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto. Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Add segment load/store intrinsics: riscv-non-isa/rvv-intrinsic-doc#198 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load): New function. (class vlseg): New class. (class vsseg): Ditto. (class vlsseg): Ditto. (class vssseg): Ditto. (class seg_indexed_load): Ditto. (class seg_indexed_store): Ditto. (class vlsegff): Ditto. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vlseg): Ditto. (vsseg): Ditto. (vlsseg): Ditto. (vssseg): Ditto. (vluxseg): Ditto. (vloxseg): Ditto. (vsuxseg): Ditto. (vsoxseg): Ditto. (vlsegff): Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct seg_loadstore_def): Ditto. (struct seg_indexed_loadstore_def): Ditto. (struct seg_fault_load_def): Ditto. (SHAPE): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (function_builder::append_nf): New function. * config/riscv/riscv-vector-builtins.def (vfloat32m1x2_t): Change ptr from double into float. (vfloat32m1x3_t): Ditto. (vfloat32m1x4_t): Ditto. (vfloat32m1x5_t): Ditto. (vfloat32m1x6_t): Ditto. (vfloat32m1x7_t): Ditto. (vfloat32m1x8_t): Ditto. (vfloat32m2x2_t): Ditto. (vfloat32m2x3_t): Ditto. (vfloat32m2x4_t): Ditto. (vfloat32m4x2_t): Ditto. * config/riscv/riscv-vector-builtins.h: Add segment intrinsics. * config/riscv/riscv-vsetvl.cc (fault_first_load_p): Adapt for segment ff load. * config/riscv/riscv.md: Add segment instructions. * config/riscv/vector-iterators.md: Support segment intrinsics. * config/riscv/vector.md (@pred_unit_strided_load<mode>): New pattern. (@pred_unit_strided_store<mode>): Ditto. (@pred_strided_load<mode>): Ditto. (@pred_strided_store<mode>): Ditto. (@pred_fault_load<mode>): Ditto. (@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto. (@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto. Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Add segment load/store intrinsics: riscv-non-isa/rvv-intrinsic-doc#198 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load): New function. (class vlseg): New class. (class vsseg): Ditto. (class vlsseg): Ditto. (class vssseg): Ditto. (class seg_indexed_load): Ditto. (class seg_indexed_store): Ditto. (class vlsegff): Ditto. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vlseg): Ditto. (vsseg): Ditto. (vlsseg): Ditto. (vssseg): Ditto. (vluxseg): Ditto. (vloxseg): Ditto. (vsuxseg): Ditto. (vsoxseg): Ditto. (vlsegff): Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct seg_loadstore_def): Ditto. (struct seg_indexed_loadstore_def): Ditto. (struct seg_fault_load_def): Ditto. (SHAPE): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (function_builder::append_nf): New function. * config/riscv/riscv-vector-builtins.def (vfloat32m1x2_t): Change ptr from double into float. (vfloat32m1x3_t): Ditto. (vfloat32m1x4_t): Ditto. (vfloat32m1x5_t): Ditto. (vfloat32m1x6_t): Ditto. (vfloat32m1x7_t): Ditto. (vfloat32m1x8_t): Ditto. (vfloat32m2x2_t): Ditto. (vfloat32m2x3_t): Ditto. (vfloat32m2x4_t): Ditto. (vfloat32m4x2_t): Ditto. * config/riscv/riscv-vector-builtins.h: Add segment intrinsics. * config/riscv/riscv-vsetvl.cc (fault_first_load_p): Adapt for segment ff load. * config/riscv/riscv.md: Add segment instructions. * config/riscv/vector-iterators.md: Support segment intrinsics. * config/riscv/vector.md (@pred_unit_strided_load<mode>): New pattern. (@pred_unit_strided_store<mode>): Ditto. (@pred_strided_load<mode>): Ditto. (@pred_strided_store<mode>): Ditto. (@pred_fault_load<mode>): Ditto. (@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto. (@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto. Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Add segment load/store intrinsics: riscv-non-isa/rvv-intrinsic-doc#198 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load): New function. (class vlseg): New class. (class vsseg): Ditto. (class vlsseg): Ditto. (class vssseg): Ditto. (class seg_indexed_load): Ditto. (class seg_indexed_store): Ditto. (class vlsegff): Ditto. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vlseg): Ditto. (vsseg): Ditto. (vlsseg): Ditto. (vssseg): Ditto. (vluxseg): Ditto. (vloxseg): Ditto. (vsuxseg): Ditto. (vsoxseg): Ditto. (vlsegff): Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct seg_loadstore_def): Ditto. (struct seg_indexed_loadstore_def): Ditto. (struct seg_fault_load_def): Ditto. (SHAPE): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (function_builder::append_nf): New function. * config/riscv/riscv-vector-builtins.def (vfloat32m1x2_t): Change ptr from double into float. (vfloat32m1x3_t): Ditto. (vfloat32m1x4_t): Ditto. (vfloat32m1x5_t): Ditto. (vfloat32m1x6_t): Ditto. (vfloat32m1x7_t): Ditto. (vfloat32m1x8_t): Ditto. (vfloat32m2x2_t): Ditto. (vfloat32m2x3_t): Ditto. (vfloat32m2x4_t): Ditto. (vfloat32m4x2_t): Ditto. * config/riscv/riscv-vector-builtins.h: Add segment intrinsics. * config/riscv/riscv-vsetvl.cc (fault_first_load_p): Adapt for segment ff load. * config/riscv/riscv.md: Add segment instructions. * config/riscv/vector-iterators.md: Support segment intrinsics. * config/riscv/vector.md (@pred_unit_strided_load<mode>): New pattern. (@pred_unit_strided_store<mode>): Ditto. (@pred_strided_load<mode>): Ditto. (@pred_strided_store<mode>): Ditto. (@pred_fault_load<mode>): Ditto. (@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto. (@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto. (@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto. (@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto. (@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto. (@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto. (@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto. (@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto. Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
This resolves #139. This change is motivated by constant unpleasant user feedback of the current segment load/store intrinsics and hope to align the interface of segment load/store intrinsics with the non-segment ones.
This PR adds the tuple-type segment load-store intrinsics and removes the existing ones. To company the tuple-types, additional
vget
andvset
intrinsics for them are added.Take
vlseg2e8
for example, these are the intrinsics added:The LLVM implementation has a proof-of-concept available: