ECP5 migration

[PhileasL]

Purpose of this PR

Simple: Not enough logic element in our test FPGA (1k for our ICE40 HX1K). The ECP5 we bought have 24k logic element which is enough for our needs.

Board used

We are currently using the colorlight i5 that got the best ratio price/performance (50€ for 24k LUTs and a development board is incredibly cheap !).

From unboxing to blink

Pretty straight forward following this amazing tutorial.

What has been change for code migration ?

Here's what matter for this PR, changes that occur in the code base.

Makefile

• make will synthesis the verilog
• make flash will flash the volatile memory
• make prog will program the onboard SPI memory

inout

Inout wire are tedious to manage. Luckily, there is a primitive that well manage it: TRELLIS_IO
Then, we just have to register data retrieved + buffer the last data received.

PLL

As the external clock on this board is 25MHz and our system is 96MHz, 2 PLL are used, one to transform 25 to 100MHz, and another to turns 100 to 96MHz and 12MHz.

Bugfix

Just a little bugfix over serial_transmitter that was resetting pulse_identifier before buffering data to send.

[PhileasL]

LGTM:
Next steps:

• Architecture refactoring
• ...