Consider renaming the avx512gfni feature to just gfni
#100752
Labels
A-target-feature
Area: Enabling/disabling target features like AVX, Neon, etc.
C-bug
Category: This is a bug.
Comments
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The same goes for |
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This.. seems incorrect. The versions that don't build off and include AVX512 should be separate features, if I remember the ad copy around these. |
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I'm not sure if you mean my suggestion is incorrect, or the existing feature names, but rustc certainly isn't the first to be confused by the new convention used here: https://community.intel.com/t5/Intel-ISA-Extensions/GFNI-documentation-anomaly/td-p/1153193 |
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I am mostly expressing bafflement at the current situation. |
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Please also see rust-lang/stdarch#1343 On AMD platform, VAES (I doubt VPCLMULQDQ) codegen would suffer from the similar issue mentioned here. |
Dylan-DPC
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Nov 16, 2022
…ilee Fix some misleading target feature aliases This is the first half of a fix for rust-lang#100752. It looks like these aliases were added in rust-lang#78361 and slipped under the radar, as these features are not AVX512. These features _do_ add AVX512 instructions when used _in combination_ with AVX512F, but without AVX512F, these features still provide 128-bit and 256-bit vector instructions. A user might be mislead into thinking these features imply AVX512F (which is true of the actual AVX512 features). This PR allows using the names as defined by LLVM, which matches Intel documentation. A future PR should change the `std::arch` intrinsics to use these names, and finally remove these aliases from rustc. r? `@workingjubilee` cc `@Amanieu`
matthiaskrgr
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…ilee Fix some misleading target feature aliases This is the first half of a fix for rust-lang#100752. It looks like these aliases were added in rust-lang#78361 and slipped under the radar, as these features are not AVX512. These features _do_ add AVX512 instructions when used _in combination_ with AVX512F, but without AVX512F, these features still provide 128-bit and 256-bit vector instructions. A user might be mislead into thinking these features imply AVX512F (which is true of the actual AVX512 features). This PR allows using the names as defined by LLVM, which matches Intel documentation. A future PR should change the `std::arch` intrinsics to use these names, and finally remove these aliases from rustc. r? ``@workingjubilee`` cc ``@Amanieu``
matthiaskrgr
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Nov 16, 2022
…ilee Fix some misleading target feature aliases This is the first half of a fix for rust-lang#100752. It looks like these aliases were added in rust-lang#78361 and slipped under the radar, as these features are not AVX512. These features _do_ add AVX512 instructions when used _in combination_ with AVX512F, but without AVX512F, these features still provide 128-bit and 256-bit vector instructions. A user might be mislead into thinking these features imply AVX512F (which is true of the actual AVX512 features). This PR allows using the names as defined by LLVM, which matches Intel documentation. A future PR should change the `std::arch` intrinsics to use these names, and finally remove these aliases from rustc. r? ```@workingjubilee``` cc ```@Amanieu```
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Aaron1011
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…ilee Fix some misleading target feature aliases This is the first half of a fix for rust-lang#100752. It looks like these aliases were added in rust-lang#78361 and slipped under the radar, as these features are not AVX512. These features _do_ add AVX512 instructions when used _in combination_ with AVX512F, but without AVX512F, these features still provide 128-bit and 256-bit vector instructions. A user might be mislead into thinking these features imply AVX512F (which is true of the actual AVX512 features). This PR allows using the names as defined by LLVM, which matches Intel documentation. A future PR should change the `std::arch` intrinsics to use these names, and finally remove these aliases from rustc. r? ```@workingjubilee``` cc ```@Amanieu```
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antoyo
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Jun 19, 2023
…ilee Fix some misleading target feature aliases This is the first half of a fix for rust-lang#100752. It looks like these aliases were added in rust-lang#78361 and slipped under the radar, as these features are not AVX512. These features _do_ add AVX512 instructions when used _in combination_ with AVX512F, but without AVX512F, these features still provide 128-bit and 256-bit vector instructions. A user might be mislead into thinking these features imply AVX512F (which is true of the actual AVX512 features). This PR allows using the names as defined by LLVM, which matches Intel documentation. A future PR should change the `std::arch` intrinsics to use these names, and finally remove these aliases from rustc. r? ```@workingjubilee``` cc ```@Amanieu```
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While GFNI has (optional) AVX-512 instructions, there is at least one microarchitecture (Tremont) that has GFNI without AVX-512.
This is further confirmed by running:
Unlike other AVX-512 features,
avx512fis not enabled, so I'm not sure this should be considered an AVX-512 feature.The text was updated successfully, but these errors were encountered: