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Set max_atomic_width for AVR to 16 #114495

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Aug 7, 2023
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@taiki-e taiki-e commented Aug 5, 2023

@rustbot rustbot added S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. labels Aug 5, 2023
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rustbot commented Aug 5, 2023

These commits modify compiler targets.
(See the Target Tier Policy.)

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The generated code disables interrupts, which doesn't seem like an operation that should happen implicitly to me. Do any other LLVM targets do this? AVR has an 8-bit data bus, so it can't support anything beyond 8-bit atomics in hardware.

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taiki-e commented Aug 5, 2023

The generated code disables interrupts, which doesn't seem like an operation that should happen implicitly to me.

AFAIK, AVR has no unprivileged mode and is always single-core, so the atomic implementation by disabling interrupts is always valid. (The situation differs somewhat from ARM and RISC-V, which have unprivileged modes.)

That said, I'm open to discarding this PR if it is considered that the compiler should not implicitly generate code to disable interrupts to implement atomics, regardless of the architecture.

Do any other LLVM targets do this?

AFAIK, it is only AVR. (However, I think atomic RMW on MSP430 possibly be implemented in the same way in the future, aside from whether the LLVM should do it.)

AVR has an 8-bit data bus, so it can't support anything beyond 8-bit atomics in hardware.

Yeah, we cannot implement 16-bit atomic on AVR without disabling interrupts (or guaranteeing atomicity in an environment-specific way). Although LLVM doesn't seem to consider 8-bit load/store instructions to be atomic either (that may be a bug, but they disable interrupts for both 8-bit and 16-bit atomic load/store).

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Amanieu commented Aug 7, 2023

@bors r+

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bors commented Aug 7, 2023

📌 Commit c9e83c0 has been approved by Amanieu

It is now in the queue for this repository.

@bors bors added S-waiting-on-bors Status: Waiting on bors to run and complete tests. Bors will change the label on completion. and removed S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. labels Aug 7, 2023
bors added a commit to rust-lang-ci/rust that referenced this pull request Aug 7, 2023
…iaskrgr

Rollup of 9 pull requests

Successful merges:

 - rust-lang#113568 (Fix spurious test failure with `panic=abort`)
 - rust-lang#114196 (Bubble up nested goals from equation in `predicates_for_object_candidate`)
 - rust-lang#114485 (Add trait decls to SMIR)
 - rust-lang#114495 (Set max_atomic_width for AVR to 16)
 - rust-lang#114496 (Set max_atomic_width for sparc-unknown-linux-gnu to 32)
 - rust-lang#114510 (llvm-wrapper: adapt for LLVM API changes)
 - rust-lang#114562 (stabilize abi_thiscall)
 - rust-lang#114570 ([miri][typo] Fix a typo in a vector_block comment.)
 - rust-lang#114573 (CI: do not hide error logs in a group)

r? `@ghost`
`@rustbot` modify labels: rollup
@bors bors merged commit b0a5126 into rust-lang:master Aug 7, 2023
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@rustbot rustbot added this to the 1.73.0 milestone Aug 7, 2023
@taiki-e taiki-e deleted the avr-atomic branch August 7, 2023 18:10
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5 participants