[LLVM][XTHeadVector] Rearrange extensions related to xtheadvector (#32)

* [LLVM][XTHeadVector] Move reference from RVV 0.7.1 to XTHeadVector 1.0

* [LLVM][NFC] Address compiler warnings

clang/test/Preprocessor/riscv-target-features.c

@@ -229,7 +229,7 @@
 // RUN: -march=rv64i_xtheadvector -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-V0P7-EXT %s
 // CHECK-V0P7-EXT: __riscv_th_v_intrinsic 11000{{$}}
-// CHECK-V0P7-EXT: __riscv_xtheadvector 7000{{$}}
+// CHECK-V0P7-EXT: __riscv_xtheadvector 1000000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
 // RUN: -march=rv32izfhmin1p0 -x c -E -dM %s \

llvm/lib/Support/RISCVISAInfo.cpp

@@ -80,15 +80,13 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
     {"xtheadmemidx", RISCVExtensionVersion{1, 0}},
     {"xtheadmempair", RISCVExtensionVersion{1, 0}},
     {"xtheadsync", RISCVExtensionVersion{1, 0}},
-    // T-Head vector extension series: Zvamo
-    {"xtheadvamo", RISCVExtensionVersion{0, 7}},
     {"xtheadvdot", RISCVExtensionVersion{1, 0}},
-    // T-Head vector extension (namely Vector extension 0.7.1) series.
-    {"xtheadvector", RISCVExtensionVersion{0, 7}},
-    // T-Head vector extension series: Zvediv
-    {"xtheadvediv", RISCVExtensionVersion{0, 7}},
-    // T-Head vector extension series: Zvlsseg
-    {"xtheadvlsseg", RISCVExtensionVersion{0, 7}},
+    // T-Head vector extension series, note:
+    // 1. The extension `Zvlsseg` (chapter 7.8) is not a subextension but a mandatory part of `XTheadVector`.
+    // 2. The `Chapter 19. Divided Element Extension ('Zvediv')` is not part of `XTheadVector`.
+    {"xtheadvector", RISCVExtensionVersion{1, 0}},
+    // 3. The extension `Zvamo` is renamed to `XTheadZvamo`.
+    {"xtheadzvamo", RISCVExtensionVersion{1, 0}},
     {"xventanacondops", RISCVExtensionVersion{1, 0}},
 
     {"zawrs", RISCVExtensionVersion{1, 0}},
@@ -960,10 +958,10 @@ Error RISCVISAInfo::checkDependency() {
     return createStringError(errc::invalid_argument,
                              "'zcf' is only supported for 'rv32'");
 
-  if (Exts.count("xtheadvamo") && !Exts.count("a"))
+  if (Exts.count("xtheadzvamo") && !Exts.count("a"))
     return createStringError(
         errc::invalid_argument,
-        "'xtheadvamo' requires 'a' extension to also be specified");
+        "'xtheadzvamo' requires 'a' extension to also be specified");
 
   if (Exts.count("xtheadvector") && HasVector)
     return createStringError(
@@ -980,7 +978,7 @@ Error RISCVISAInfo::checkDependency() {
 static const char *ImpliedExtsD[] = {"f"};
 static const char *ImpliedExtsF[] = {"zicsr"};
 static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"};
-static const char *ImpliedExtsXTHeadVamo[] = {"a"};
+static const char *ImpliedExtsXTHeadZvamo[] = {"a"};
 static const char *ImpliedExtsXTHeadVdot[] = {"v"};
 static const char *ImpliedExtsXsfvcp[] = {"zve32x"};
 static const char *ImpliedExtsZacas[] = {"a"};
@@ -1048,8 +1046,8 @@ static constexpr ImpliedExtsEntry ImpliedExts[] = {
     {{"f"}, {ImpliedExtsF}},
     {{"v"}, {ImpliedExtsV}},
     {{"xsfvcp"}, {ImpliedExtsXsfvcp}},
-    {{"xtheadvamo"}, {ImpliedExtsXTHeadVamo}},
     {{"xtheadvdot"}, {ImpliedExtsXTHeadVdot}},
+    {{"xtheadzvamo"}, {ImpliedExtsXTHeadZvamo}},
     {{"zacas"}, {ImpliedExtsZacas}},
     {{"zcb"}, {ImpliedExtsZcb}},
     {{"zcd"}, {ImpliedExtsZcd}},

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -893,7 +893,7 @@ def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
     "that allows a memory tag in the upper address bits">;
 
 //===----------------------------------------------------------------------===//
-// T-Head in RuyiSDK specific features and extensions (mostly rvv 0.7.1)
+// T-Head Vector in RuyiSDK specific features and extensions
 //===----------------------------------------------------------------------===//
 
 def FeatureVendorXTHeadV
@@ -903,27 +903,13 @@ def HasVendorXTHeadV : Predicate<"Subtarget->hasVendorXTHeadV()">,
                                   AssemblerPredicate<(all_of FeatureVendorXTHeadV),
                                   "'xtheadvector' (T-Head Base Vector Instructions)">;
 
-def FeatureVendorXTHeadVlsseg
-    : SubtargetFeature<"xtheadvlsseg", "HasVendorXTHeadVlsseg", "true",
-                       "'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions)">;
-def HasVendorXTHeadVlsseg : Predicate<"Subtarget->hasVendorXTHeadVlsseg()">,
-                                      AssemblerPredicate<(all_of FeatureVendorXTHeadVlsseg),
-                                      "'xtheadvlsseg' (T-Head Vector Load/Store Segment Instructions)">;
-
-def FeatureVendorXTHeadVamo
-    : SubtargetFeature<"xtheadvamo", "HasVendorXTHeadVamo", "true",
-                       "'xtheadvamo' (T-Head Vector AMO Operations)",
+def FeatureVendorXTHeadZvamo
+    : SubtargetFeature<"xtheadzvamo", "HasVendorXTHeadZvamo", "true",
+                       "'xtheadzvamo' (T-Head Vector AMO Operations)",
                        [FeatureStdExtA]>;
-def HasVendorXTHeadVamo : Predicate<"Subtarget->hasVendorXTHeadVamo()">,
-                                    AssemblerPredicate<(all_of FeatureVendorXTHeadVamo),
-                                    "'xtheadvamo' (T-Head Vector AMO Operations)">;
-
-def FeatureVendorXTHeadVediv
-    : SubtargetFeature<"xtheadvediv", "HasVendorXTHeadVediv", "true",
-                       "'xtheadvediv' (T-Head Divided Element Extension)">;
-def HasVendorXTHeadVediv : Predicate<"Subtarget->hasVendorXTHeadVediv()">,
-                                     AssemblerPredicate<(all_of FeatureVendorXTHeadVediv),
-                                     "'xtheadvediv' (T-Head Divided Element Extension)">;
+def HasVendorXTHeadZvamo : Predicate<"Subtarget->hasVendorXTHeadZvamo()">,
+                                     AssemblerPredicate<(all_of FeatureVendorXTHeadZvamo),
+                                     "'xtheadzvamo' (T-Head Vector AMO Operations)">;
 
 // Predicates for reusing instructions/intrinsics in both RVV 1.0 and 0.7
 def HasStdVOrXTHeadV    : Predicate<"Subtarget->hasStdVOrXTHeadV()">,

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -14687,7 +14687,6 @@ static MachineBasicBlock *emitXWholeMove(MachineInstr &MI,
   DebugLoc DL = MI.getDebugLoc();
 
   auto *TII = BB->getParent()->getSubtarget().getInstrInfo();
-  auto *MRI = &BB->getParent()->getRegInfo();
   auto *TRI = BB->getParent()->getSubtarget().getRegisterInfo();
 
   // From RVV Spec 1.0:

llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td

@@ -324,7 +324,8 @@ def TH_VLWUFF_V : TH_VLxUFF<0b000, 0b110, "th.vlwuff.v">;
 def TH_VLEFF_V : TH_VLxUFF<0b000, 0b111, "th.vleff.v">;
 } // Predicates = [HasVendorXTHeadV]
 
-let Predicates = [HasVendorXTHeadV, HasVendorXTHeadVlsseg] in {
+// The extension `Zvlsseg (chapter 7.8)` is not a subextension but a mandatory part of `XTheadVector`.
+let Predicates = [HasVendorXTHeadV] in {
 foreach nf=2-8 in {
   // Vector Unit-Stride Segment Loads and Stores
   def TH_VLSEG#nf#B_V : TH_VLx<!add(nf, -1), 0b000, "th.vlseg"#nf#"b.v">;
@@ -372,9 +373,10 @@ foreach nf=2-8 in {
   def TH_VSXSEG#nf#W_V : TH_VSXx<!add(nf, -1), 0b110, "th.vsxseg"#nf#"w.v">;
   def TH_VSXSEG#nf#E_V : TH_VSXx<!add(nf, -1), 0b111, "th.vsxseg"#nf#"e.v">;
 }
-} // Predicates = [HasVendorXTHeadV, HasVendorXTHeadVlsseg]
+} // Predicates = [HasVendorXTHeadV]
 
-let Predicates = [HasVendorXTHeadV, HasVendorXTHeadVamo, HasStdExtA] in {
+// The extension `Zvamo` is renamed to `XTheadZvamo`.
+let Predicates = [HasVendorXTHeadV, HasVendorXTHeadZvamo, HasStdExtA] in {
   // Vector AMO Instruction
   defm TH_VAMOSWAPW : TH_VAMO<0b00001, 0b110, "th.vamoswapw.v">;
   defm TH_VAMOADDW : TH_VAMO<0b00000, 0b110, "th.vamoaddw.v">;
@@ -405,7 +407,7 @@ let Predicates = [HasVendorXTHeadV, HasVendorXTHeadVamo, HasStdExtA] in {
   defm TH_VAMOMAXQ : TH_VAMO<0b10100, 0b000, "th.vamomaxq.v">;
   defm TH_VAMOMINUQ : TH_VAMO<0b11000, 0b000, "th.vamominuq.v">;
   defm TH_VAMOMAXUQ : TH_VAMO<0b11100, 0b000, "th.vamomaxuq.v">;
-} // Predicates = [HasVendorXTHeadV, HasVendorXTHeadVamo, HasStdExtA]
+} // Predicates = [HasVendorXTHeadV, HasVendorXTHeadZvamo, HasStdExtA]
 
 let Predicates = [HasVendorXTHeadV] in {
 // Vector Single-Width Integer Add and Subtract

llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td

@@ -850,7 +850,7 @@ multiclass XVPseudoAMO {
   defm "D" : XVPseudoAMOMem<64>;
 }
 
-let Predicates = [HasVendorXTHeadV, HasVendorXTHeadVamo, HasStdExtA] in {
+let Predicates = [HasVendorXTHeadV, HasVendorXTHeadZvamo, HasStdExtA] in {
   defm PseudoTH_VAMOSWAP : XVPseudoAMO;
   defm PseudoTH_VAMOADD  : XVPseudoAMO;
   defm PseudoTH_VAMOXOR  : XVPseudoAMO;
@@ -860,7 +860,7 @@ let Predicates = [HasVendorXTHeadV, HasVendorXTHeadVamo, HasStdExtA] in {
   defm PseudoTH_VAMOMAX  : XVPseudoAMO;
   defm PseudoTH_VAMOMINU : XVPseudoAMO;
   defm PseudoTH_VAMOMAXU : XVPseudoAMO;
-} // Predicates = [HasVendorXTHeadV, HasVendorXTHeadVamo, HasStdExtA]
+} // Predicates = [HasVendorXTHeadV, HasVendorXTHeadZvamo, HasStdExtA]
 
 // Patterns for vamo intrinsics.
 class XVPatAMOWDNoMask<string intrinsic_name,
@@ -938,7 +938,7 @@ multiclass XVPatAMOV_WD<string intrinsic,
   }
 }
 
-let Predicates = [HasVendorXTHeadV, HasVendorXTHeadVamo, HasStdExtA] in {
+let Predicates = [HasVendorXTHeadV, HasVendorXTHeadZvamo, HasStdExtA] in {
   defm : XVPatAMOV_WD<"int_riscv_th_vamoswap", "PseudoTH_VAMOSWAP", AllIntegerXVectors>;
   defm : XVPatAMOV_WD<"int_riscv_th_vamoadd", "PseudoTH_VAMOADD", AllIntegerXVectors>;
   defm : XVPatAMOV_WD<"int_riscv_th_vamoxor", "PseudoTH_VAMOXOR", AllIntegerXVectors>;
@@ -948,7 +948,7 @@ let Predicates = [HasVendorXTHeadV, HasVendorXTHeadVamo, HasStdExtA] in {
   defm : XVPatAMOV_WD<"int_riscv_th_vamomax", "PseudoTH_VAMOMAX", AllIntegerXVectors>;
   defm : XVPatAMOV_WD<"int_riscv_th_vamominu", "PseudoTH_VAMOMINU", AllIntegerXVectors>;
   defm : XVPatAMOV_WD<"int_riscv_th_vamomaxu", "PseudoTH_VAMOMAXU", AllIntegerXVectors>;
-} // Predicates = [HasVendorXTHeadV, HasVendorXTHeadVamo, HasStdExtA]
+} // Predicates = [HasVendorXTHeadV, HasVendorXTHeadZvamo, HasStdExtA]
 
 //===----------------------------------------------------------------------===//
 // 12. Vector Integer Arithmetic Instructions

llvm/test/CodeGen/RISCV/rvv0p71/vamoadd.ll

@@ -1,6 +1,6 @@
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadvamo \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadzvamo \
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadvamo \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadzvamo \
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT
 
 declare <vscale x 2 x i32> @llvm.riscv.th.vamoadd.nxv2i32.nxv2i32(

llvm/test/CodeGen/RISCV/rvv0p71/vamoand.ll

@@ -1,6 +1,6 @@
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadvamo \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadzvamo \
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadvamo \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadzvamo \
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT
 
 declare <vscale x 2 x i32> @llvm.riscv.th.vamoand.nxv2i32.nxv2i32(

llvm/test/CodeGen/RISCV/rvv0p71/vamomax.ll

@@ -1,6 +1,6 @@
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadvamo \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadzvamo \
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadvamo \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadzvamo \
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT
 
 declare <vscale x 2 x i32> @llvm.riscv.th.vamomax.nxv2i32.nxv2i32(

llvm/test/CodeGen/RISCV/rvv0p71/vamomaxu.ll

@@ -1,6 +1,6 @@
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadvamo \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadzvamo \
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadvamo \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadzvamo \
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT
 
 declare <vscale x 2 x i32> @llvm.riscv.th.vamomaxu.nxv2i32.nxv2i32(

llvm/test/CodeGen/RISCV/rvv0p71/vamomin.ll

@@ -1,6 +1,6 @@
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadvamo \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadzvamo \
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadvamo \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadzvamo \
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT
 
 declare <vscale x 2 x i32> @llvm.riscv.th.vamomin.nxv2i32.nxv2i32(

llvm/test/CodeGen/RISCV/rvv0p71/vamominu.ll

@@ -1,6 +1,6 @@
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadvamo \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadzvamo \
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadvamo \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadzvamo \
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT
 
 declare <vscale x 2 x i32> @llvm.riscv.th.vamominu.nxv2i32.nxv2i32(

llvm/test/CodeGen/RISCV/rvv0p71/vamoor.ll

@@ -1,6 +1,6 @@
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadvamo \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadzvamo \
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadvamo \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadzvamo \
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT
 
 declare <vscale x 2 x i32> @llvm.riscv.th.vamoor.nxv2i32.nxv2i32(

llvm/test/CodeGen/RISCV/rvv0p71/vamoswap.ll

@@ -1,6 +1,6 @@
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadvamo \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadzvamo \
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadvamo \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadzvamo \
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT
 
 declare <vscale x 2 x i32> @llvm.riscv.th.vamoswap.nxv2i32.nxv2i32(

llvm/test/CodeGen/RISCV/rvv0p71/vamoxor.ll

@@ -1,6 +1,6 @@
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadvamo \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+a,+xtheadvector,+xtheadzvamo \
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadvamo \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+a,+xtheadvector,+xtheadzvamo \
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LABEL,CHECK-NEXT
 
 declare <vscale x 2 x i32> @llvm.riscv.th.vamoxor.nxv2i32.nxv2i32(

llvm/test/MC/RISCV/attribute-arch.s

@@ -292,14 +292,14 @@
 # CHECK: attribute      5, "rv32i2p1_xcvmac1p0"
 
 .attribute arch, "rv32i_xtheadvector"
-# CHECK: attribute      5, "rv32i2p1_xtheadvector0p7"
+# CHECK: attribute      5, "rv32i2p1_xtheadvector1p0"
 
-.attribute arch, "rv32i_xtheadvector_xtheadvamo_xtheadvediv_xtheadvlsseg"
-# CHECK: attribute      5, "rv32i2p1_a2p1_xtheadvamo0p7_xtheadvector0p7_xtheadvediv0p7_xtheadvlsseg0p7"
+.attribute arch, "rv32i_xtheadvector_xtheadzvamo"
+# CHECK: attribute      5, "rv32i2p1_a2p1_xtheadvector1p0_xtheadzvamo1p0"
 
 .attribute arch, "rv32i_xtheadvector"
-# CHECK: attribute      5, "rv32i2p1_xtheadvector0p7"
+# CHECK: attribute      5, "rv32i2p1_xtheadvector1p0"
 
-.attribute arch, "rv64i_xtheadvector_xtheadvamo_xtheadvediv_xtheadvlsseg"
-# CHECK: attribute      5, "rv64i2p1_a2p1_xtheadvamo0p7_xtheadvector0p7_xtheadvediv0p7_xtheadvlsseg0p7"
+.attribute arch, "rv64i_xtheadvector_xtheadzvamo"
+# CHECK: attribute      5, "rv64i2p1_a2p1_xtheadvector1p0_xtheadzvamo1p0"
 

llvm/test/MC/RISCV/rvv0p71/vector-insns.s

@@ -2,7 +2,7 @@
 # Golden value for this test: https://github.com/riscvarchive/riscv-binutils-gdb/blob/1aeeeab05f3c39e2bfc6e99384490d4c7f484ba0/gas/testsuite/gas/riscv/vector-insns.d
 # Generated using the script: https://gist.github.com/imkiva/05facf1a51ff8abfeeeea8fa7bc307ad#file-rvvtestgen-java
 
-# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+f,+a,+xtheadvector,+xtheadvlsseg,+xtheadvamo %s \
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+f,+a,+xtheadvector,+xtheadzvamo %s \
 # RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 
 th.vsetvl a0, a1, a2