Merge pull request #117 from slaclab/datagpu-dev

Major Update: increasing AXI4 memory address from 40-bits to 64-bits
slaclab · Jul 25, 2024 · f2b5546 · f2b5546
2 parents 5d0e639 + c1918e8
commit f2b5546
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Showing 240 changed files with 2,612 additions and 10,490 deletions.
diff --git a/hardware/AbacoPc821/pcie/ip/AbacoPc821PciePhy.dcp b/hardware/AbacoPc821/pcie/ip/AbacoPc821PciePhy.dcp
diff --git a/hardware/AbacoPc821/pcie/ip/AbacoPc821PciePhy.xci b/hardware/AbacoPc821/pcie/ip/AbacoPc821PciePhy.xci
@@ -14,7 +14,7 @@
         "pl_link_cap_max_link_width": [ { "value": "X8", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "pl_link_cap_max_link_speed": [ { "value": "8.0_GT/s", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "ref_clk_freq": [ { "value": "100_MHz", "resolve_type": "user", "usage": "all" } ],
-        "axi_addr_width": [ { "value": "40", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "axi_addr_width": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "axi_data_width": [ { "value": "256_bit", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "coreclk_freq": [ { "value": "500", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "plltype": [ { "value": "QPLL1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
@@ -103,7 +103,7 @@
         "axibar_3": [ { "value": "0x0000000000000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "axibar_4": [ { "value": "0x0000000000000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "axibar_5": [ { "value": "0x0000000000000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "axibar_highaddr_0": [ { "value": "0xFFFFFFFFFF", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "axibar_highaddr_0": [ { "value": "0xFFFFFFFFFFFFFFFF", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "axibar_highaddr_1": [ { "value": "0x0000000000000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "axibar_highaddr_2": [ { "value": "0x0000000000000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "axibar_highaddr_3": [ { "value": "0x0000000000000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
@@ -181,7 +181,7 @@
         "PL_LINK_CAP_MAX_LINK_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "PL_LINK_CAP_MAX_LINK_SPEED": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "REF_CLK_FREQ": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "AXI_ADDR_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "AXI_DATA_WIDTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "CORE_CLK_FREQ": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "PLL_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -242,7 +242,7 @@
         "C_AXIBAR_3": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_AXIBAR_4": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_AXIBAR_5": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
-        "C_AXIBAR_HIGHADDR_0": [ { "value": "0x000000FFFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_AXIBAR_HIGHADDR_0": [ { "value": "0xFFFFFFFFFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_AXIBAR_HIGHADDR_1": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_AXIBAR_HIGHADDR_2": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_AXIBAR_HIGHADDR_3": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
@@ -333,7 +333,7 @@
         "sys_clk_gt": [ { "direction": "in", "driver_value": "0" } ],
         "intx_msi_request": [ { "direction": "in", "driver_value": "0" } ],
         "s_axi_awid": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
-        "s_axi_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_awaddr": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
         "s_axi_awregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
         "s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
         "s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
@@ -346,7 +346,7 @@
         "s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
         "s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
         "s_axi_arid": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
-        "s_axi_araddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_araddr": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
         "s_axi_arregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
         "s_axi_arlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
         "s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
@@ -395,7 +395,7 @@
         "s_axi_rlast": [ { "direction": "out" } ],
         "s_axi_rvalid": [ { "direction": "out" } ],
         "m_axi_awid": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
-        "m_axi_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
+        "m_axi_awaddr": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
         "m_axi_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
         "m_axi_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
         "m_axi_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
@@ -410,7 +410,7 @@
         "m_axi_wvalid": [ { "direction": "out" } ],
         "m_axi_bready": [ { "direction": "out" } ],
         "m_axi_arid": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
-        "m_axi_araddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
+        "m_axi_araddr": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
         "m_axi_arlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
         "m_axi_arsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
         "m_axi_arburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
@@ -629,7 +629,7 @@
             "PROTOCOL": [ { "value": "AXI4", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
             "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "ID_WIDTH": [ { "value": "3", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "ADDR_WIDTH": [ { "value": "40", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "WUSER_WIDTH": [ { "value": "32", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -706,7 +706,7 @@
             "PROTOCOL": [ { "value": "AXI4", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
             "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "ID_WIDTH": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "ADDR_WIDTH": [ { "value": "40", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "WUSER_WIDTH": [ { "value": "32", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -794,8 +794,8 @@
       },
       "address_spaces": {
         "M_AXI": {
-          "range": "1099511627776",
-          "width": "40"
+          "range": "16777216T",
+          "width": "64"
         }
       },
       "memory_maps": {

diff --git a/hardware/AbacoPc821/pcie/rtl/AbacoPc821PciePhyWrapper.vhd b/hardware/AbacoPc821/pcie/rtl/AbacoPc821PciePhyWrapper.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : AbacoPc821PciePhyWrapper.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Wrapper for AXI PCIe Core
@@ -16,7 +15,6 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiPkg.all;

diff --git a/hardware/AbacoPc821/rtl/KU085/AxiPciePkg.vhd b/hardware/AbacoPc821/rtl/KU085/AxiPciePkg.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : AxiPciePkg.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Package file for AXI PCIe Core
@@ -34,7 +33,7 @@ package AxiPciePkg is
 
    -- PCIE PHY AXI Configuration
    constant AXI_PCIE_CONFIG_C : AxiConfigType := (
-      ADDR_WIDTH_C => 40,               -- 40-bit address interface
+      ADDR_WIDTH_C => 64,               -- 64-bit address interface
       DATA_BYTES_C => 32,               -- 256-bit data interface
       ID_BITS_C    => 4,                -- Up to 16 DMA IDS
       LEN_BITS_C   => 8);               -- 8-bit awlen/arlen interface

diff --git a/hardware/AbacoPc821/rtl/KU115/AxiPciePkg.vhd b/hardware/AbacoPc821/rtl/KU115/AxiPciePkg.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : AxiPciePkg.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Package file for AXI PCIe Core
@@ -34,7 +33,7 @@ package AxiPciePkg is
 
    -- PCIE PHY AXI Configuration
    constant AXI_PCIE_CONFIG_C : AxiConfigType := (
-      ADDR_WIDTH_C => 40,               -- 40-bit address interface
+      ADDR_WIDTH_C => 64,               -- 64-bit address interface
       DATA_BYTES_C => 32,               -- 256-bit data interface
       ID_BITS_C    => 4,                -- Up to 16 DMA IDS
       LEN_BITS_C   => 8);               -- 8-bit awlen/arlen interface

diff --git a/hardware/AlphaDataKu3/pcie/ip/AlphaDataKu3PciePhy.dcp b/hardware/AlphaDataKu3/pcie/ip/AlphaDataKu3PciePhy.dcp