Chnaged lane num to 8 (DAC has upto 8). Added laneEnable register

slaclab · Apr 24, 2024 · acfc6ed · acfc6ed
1 parent 6995288
commit acfc6ed
Showing 1 changed file with 9 additions and 1 deletion.
diff --git a/yaml/Dac38J84.yaml b/yaml/Dac38J84.yaml
@@ -16,7 +16,7 @@ Dac38J84: &Dac38J84
   class: MMIODev
   configPrio: 1
   metadata:
-    numTxLanes: &numTxLanes 2
+    numTxLanes: &numTxLanes 8
   children:
     #########################################################
     DacReg:
@@ -29,6 +29,14 @@ Dac38J84: &Dac38J84
       mode:         RW
       description:  DAC Registers[125:0]
     #########################################################
+    LaneEnable:
+      at:
+        offset:     0x129
+      class:        IntField
+      sizeBits:     8
+      mode:         RO
+      description:  Lane Enable
+    #########################################################
     LaneBufferDelay:
       at:
         offset:     0x01C