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Merge pull request #1082 from slaclab/xvc-wrapper
Xvc wrapper merge
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------------------------------------------------------------------------------- | ||
-- Company : SLAC National Accelerator Laboratory | ||
------------------------------------------------------------------------------- | ||
-- Description: XVC Wrapper | ||
------------------------------------------------------------------------------- | ||
-- This file is part of 'SLAC Firmware Standard Library'. | ||
-- It is subject to the license terms in the LICENSE.txt file found in the | ||
-- top-level directory of this distribution and at: | ||
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. | ||
-- No part of 'SLAC Firmware Standard Library', including this file, | ||
-- may be copied, modified, propagated, or distributed except according to | ||
-- the terms contained in the LICENSE.txt file. | ||
------------------------------------------------------------------------------- | ||
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library ieee; | ||
use ieee.std_logic_1164.all; | ||
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library surf; | ||
use surf.StdRtlPkg.all; | ||
use surf.AxiStreamPkg.all; | ||
use surf.EthMacPkg.all; | ||
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entity PgpXvcWrapper is | ||
generic ( | ||
TPD_G : time := 1 ns; | ||
SIMULATION_G : boolean := false; | ||
AXIS_CLK_FREQ_G : real := 156.25e6; | ||
PHY_AXI_CONFIG_G : AxiStreamConfigType); | ||
port ( | ||
-- Clock and Reset (xvcClk domain) | ||
xvcClk : in sl; | ||
xvcRst : in sl; | ||
-- Clock and Reset (pgpClk domain) | ||
pgpClk : in sl; | ||
pgpRst : in sl; | ||
-- PGP Interface (pgpClk domain) | ||
rxlinkReady : in sl; | ||
txlinkReady : in sl; | ||
-- TX FIFO (pgpClk domain) | ||
pgpTxSlave : in AxiStreamSlaveType; | ||
pgpTxMaster : out AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; | ||
-- RX FIFO (pgpClk domain) | ||
pgpRxMaster : in AxiStreamMasterType; | ||
pgpRxCtrl : out AxiStreamCtrlType := AXI_STREAM_CTRL_UNUSED_C); | ||
end PgpXvcWrapper; | ||
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architecture rtl of PgpXvcWrapper is | ||
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signal ibXvcMaster : AxiStreamMasterType := axiStreamMasterInit(EMAC_AXIS_CONFIG_C); | ||
signal ibXvcSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; | ||
signal obXvcMaster : AxiStreamMasterType := axiStreamMasterInit(EMAC_AXIS_CONFIG_C); | ||
signal obXvcSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; | ||
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begin | ||
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GEN_REAL : if (SIMULATION_G = false) generate | ||
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----------------------------------------------------------------- | ||
-- Xilinx Virtual Cable (XVC) | ||
-- https://www.xilinx.com/products/intellectual-property/xvc.html | ||
----------------------------------------------------------------- | ||
U_XVC : entity surf.UdpDebugBridgeWrapper | ||
generic map ( | ||
TPD_G => TPD_G, | ||
AXIS_CLK_FREQ_G => AXIS_CLK_FREQ_G) | ||
port map ( | ||
-- Clock and Reset | ||
clk => xvcClk, | ||
rst => xvcRst, | ||
-- UDP XVC Interface | ||
obServerMaster => ibXvcMaster, | ||
obServerSlave => ibXvcSlave, | ||
ibServerMaster => obXvcMaster, | ||
ibServerSlave => obXvcSlave); | ||
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U_VC_RX : entity surf.PgpRxVcFifo | ||
generic map ( | ||
TPD_G => TPD_G, | ||
PHY_AXI_CONFIG_G => PHY_AXI_CONFIG_G, | ||
APP_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C) | ||
port map ( | ||
-- PGP Interface (pgpClk domain) | ||
pgpClk => pgpClk, | ||
pgpRst => pgpRst, | ||
rxlinkReady => rxlinkReady, | ||
pgpRxMaster => pgpRxMaster, | ||
pgpRxCtrl => pgpRxCtrl, | ||
pgpRxSlave => pgpRxSlave, | ||
-- AXIS Interface (axisClk domain) | ||
axisClk => xvcClk, | ||
axisRst => xvcRst, | ||
axisMaster => ibXvcMaster, | ||
axisSlave => ibXvcSlave); | ||
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U_VC_TX : entity surf.PgpTxVcFifo | ||
generic map ( | ||
TPD_G => TPD_G, | ||
APP_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C, | ||
PHY_AXI_CONFIG_G => PHY_AXI_CONFIG_G) | ||
port map ( | ||
-- AXIS Interface (axisClk domain) | ||
axisClk => xvcClk, | ||
axisRst => xvcRst, | ||
axisMaster => obXvcMaster, | ||
axisSlave => obXvcSlave, | ||
-- PGP Interface (pgpClk domain) | ||
pgpClk => pgpClk, | ||
pgpRst => pgpRst, | ||
rxlinkReady => rxlinkReady, | ||
txlinkReady => txlinkReady, | ||
pgpTxMaster => pgpTxMaster, | ||
pgpTxSlave => pgpTxSlave); | ||
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end generate GEN_REAL; | ||
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end rtl; |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,136 @@ | ||
------------------------------------------------------------------------------- | ||
-- Company : SLAC National Accelerator Laboratory | ||
------------------------------------------------------------------------------- | ||
-- Description: XVC Wrapper | ||
------------------------------------------------------------------------------- | ||
-- This file is part of 'SLAC Firmware Standard Library'. | ||
-- It is subject to the license terms in the LICENSE.txt file found in the | ||
-- top-level directory of this distribution and at: | ||
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. | ||
-- No part of 'SLAC Firmware Standard Library', including this file, | ||
-- may be copied, modified, propagated, or distributed except according to | ||
-- the terms contained in the LICENSE.txt file. | ||
------------------------------------------------------------------------------- | ||
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library ieee; | ||
use ieee.std_logic_1164.all; | ||
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library surf; | ||
use surf.StdRtlPkg.all; | ||
use surf.AxiStreamPkg.all; | ||
use surf.EthMacPkg.all; | ||
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library unisim; | ||
use unisim.vcomponents.all; | ||
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entity DmaXvcWrapper is | ||
generic ( | ||
TPD_G : time := 1 ns; | ||
COMMON_CLOCK_G : boolean := false; | ||
AXIS_CLK_FREQ_G : real := 156.25e6; | ||
FIFO_INT_PIPE_STAGES_G : natural range 0 to 16 := 0; -- Internal FIFO setting | ||
FIFO_PIPE_STAGES_G : natural range 0 to 16 := 1; | ||
OB_FIFO_SLAVE_READY_EN_G : boolean := true; | ||
FIFO_ADDR_WIDTH_G : integer range 4 to 48 := 9; | ||
FIFO_SYNTH_MODE_G : string := "inferred"; | ||
FIFO_MEMORY_TYPE_G : string := "block"; | ||
AXIS_CONFIG_G : AxiStreamConfigType); | ||
port ( | ||
-- Clock and Reset (xvcClk domain) | ||
xvcClk : in sl; | ||
xvcRst : in sl; | ||
-- Clock and Reset (axisClk domain) | ||
axisClk : in sl; | ||
axisRst : in sl; | ||
-- OB FIFO (axisClk domain) | ||
obFifoMaster : in AxiStreamMasterType; | ||
obFifoSlave : out AxiStreamSlaveType; | ||
obFifoCtrl : out AxiStreamCtrlType; | ||
-- IB FIFO (axisClk domain) | ||
ibFifoSlave : in AxiStreamSlaveType; | ||
ibFifoMaster : out AxiStreamMasterType); | ||
end DmaXvcWrapper; | ||
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architecture rtl of DmaXvcWrapper is | ||
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signal ibXvcMaster : AxiStreamMasterType := axiStreamMasterInit(EMAC_AXIS_CONFIG_C); | ||
signal ibXvcSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; | ||
signal obXvcMaster : AxiStreamMasterType := axiStreamMasterInit(EMAC_AXIS_CONFIG_C); | ||
signal obXvcSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; | ||
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begin | ||
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----------------------------------------------------------------- | ||
-- Xilinx Virtual Cable (XVC) | ||
-- https://www.xilinx.com/products/intellectual-property/xvc.html | ||
----------------------------------------------------------------- | ||
U_XVC : entity surf.UdpDebugBridgeWrapper | ||
generic map ( | ||
TPD_G => TPD_G, | ||
AXIS_CLK_FREQ_G => AXIS_CLK_FREQ_G) | ||
port map ( | ||
-- Clock and Reset | ||
clk => xvcClk, | ||
rst => xvcRst, | ||
-- UDP XVC Interface | ||
obServerMaster => obXvcMaster, | ||
obServerSlave => obXvcSlave, | ||
ibServerMaster => ibXvcMaster, | ||
ibServerSlave => ibXvcSlave); | ||
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U_OB_FIFO : entity surf.AxiStreamFifoV2 | ||
generic map ( | ||
-- General Configurations | ||
TPD_G => TPD_G, | ||
-- FIFO configurations | ||
INT_PIPE_STAGES_G => FIFO_INT_PIPE_STAGES_G, | ||
PIPE_STAGES_G => FIFO_PIPE_STAGES_G, | ||
SLAVE_READY_EN_G => OB_FIFO_SLAVE_READY_EN_G, | ||
GEN_SYNC_FIFO_G => COMMON_CLOCK_G, | ||
MEMORY_TYPE_G => FIFO_MEMORY_TYPE_G, | ||
FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, | ||
SYNTH_MODE_G => FIFO_SYNTH_MODE_G, | ||
-- AXI Stream Port Configurations | ||
SLAVE_AXI_CONFIG_G => AXIS_CONFIG_G, | ||
MASTER_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C) | ||
port map ( | ||
-- Slave Port | ||
sAxisClk => axisClk, | ||
sAxisRst => axisRst, | ||
sAxisMaster => obFifoMaster, | ||
sAxisSlave => obFifoSlave, | ||
sAxisCtrl => obFifoCtrl, | ||
-- Master Port | ||
mAxisClk => xvcClk, | ||
mAxisRst => xvcRst, | ||
mAxisMaster => obXvcMaster, | ||
mAxisSlave => obXvcSlave); | ||
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U_IB_FIFO : entity surf.AxiStreamFifoV2 | ||
generic map ( | ||
-- General Configurations | ||
TPD_G => TPD_G, | ||
-- FIFO configurations | ||
INT_PIPE_STAGES_G => FIFO_INT_PIPE_STAGES_G, | ||
PIPE_STAGES_G => FIFO_PIPE_STAGES_G, | ||
SLAVE_READY_EN_G => OB_FIFO_SLAVE_READY_EN_G, | ||
GEN_SYNC_FIFO_G => COMMON_CLOCK_G, | ||
MEMORY_TYPE_G => FIFO_MEMORY_TYPE_G, | ||
FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, | ||
SYNTH_MODE_G => FIFO_SYNTH_MODE_G, | ||
-- AXI Stream Port Configurations | ||
SLAVE_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C, | ||
MASTER_AXI_CONFIG_G => AXIS_CONFIG_G) | ||
port map ( | ||
-- Slave Port | ||
sAxisClk => xvcClk, | ||
sAxisRst => xvcRst, | ||
sAxisMaster => ibXvcMaster, | ||
sAxisSlave => ibXvcSlave, | ||
-- Master Port | ||
mAxisClk => axisClk, | ||
mAxisRst => axisRst, | ||
mAxisMaster => ibFifoMaster, | ||
mAxisSlave => ibFifoSlave); | ||
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end rtl; |
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