Create ADS1217 ADC

[hsandber]

Description

Created ADS1217 ADC VHDL module and with matching Python class.

Details

Created a new AxiAds1217Core VHDL module with AXI4-Lite register access to ADC data for all channels.
This is a generalized version of modules that have been used in various projects, see for example:

• epix-hr-core
• epix
• epix-daq-gen2-core
• epix-hr-single-Mv2

JIRA

Related

[hsandber]

This ADC module only has AXI4-Lite access to the ADC data right now. In some previous applications there has been an AXI4-Stream interface also, which has not been implemented in this generic version of the module yet.

@ruck314, would you prefer to wait until a final version is available with both Lite and Stream interface, or would it better to get this "simpler" version merged in now? I do not have a time estimate for when the final version could be ready.

[ruck314]

@ruck314, would you prefer to wait until a final version is available with both Lite and Stream interface, or would it better to get this "simpler" version merged in now? I do not have a time estimate for when the final version could be ready.

@bengineerd Do you want to wait for the stream version of this?

[bengineerd]

@hsandber hsandber AxiAds1217Core.vhd does not follow the "two process" coding style for the sysClk registers.

[hsandber]

@bengineerd Do you prefer we close this pull request and delete the branch and then come back at "some point in the future" when the module has been rewritten to match the firmware standards for surf?