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Feature - Product/Quotient/Remainder (PQR) Instruction Class #498
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Codecov Report
@@ Coverage Diff @@
## main #498 +/- ##
==========================================
- Coverage 89.55% 89.30% -0.26%
==========================================
Files 23 23
Lines 10119 10283 +164
==========================================
+ Hits 9062 9183 +121
- Misses 1057 1100 +43
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We don't use the original BPF backend of LLVM, since we have a separate SBF backend https://github.com/solana-labs/llvm-project/tree/7b8db05b564faffb522434b73b7082662171f94a/llvm/lib/Target/SBF |
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There is still an ongoing discussion about if we want to keep sign extension: solana-labs/solana#32924 And we are still missing a test for all the deprecated features. But that will go into another PR. |
Multiplications and divisions will get a new more uniform and versatile instruction encoding in SBPFv2.
Scheme of the instruction encoding:
0
1
Instructions of the new
BPF_PQR
class:06
/00000110
0E
/00001110
16
/00010110
1E
/00011110
26
/00100110
2E
/00101110
36
/00110110
BPF_UHMUL64_IMM
uhmul64 dst, imm
3E
/00111110
BPF_UHMUL64_REG
uhmul64 dst, src
46
/01000110
BPF_UDIV32_IMM
udiv32 dst, imm
34
/BPF_DIV32_IMM
/div32 dst, imm
4E
/01001110
BPF_UDIV32_REG
udiv32 dst, src
3C
/BPF_DIV32_REG
/div32 dst, src
56
/01010110
BPF_UDIV64_IMM
udiv64 dst, imm
37
/BPF_DIV64_IMM
/div64 dst, imm
5E
/01011110
BPF_UDIV64_REG
udiv64 dst, src
3F
/BPF_DIV64_REG
/div64 dst, src
66
/01100110
BPF_UREM32_IMM
urem32 dst, imm
94
/BPF_MOD32_IMM
/mod32 dst, imm
6E
/01101110
BPF_UREM32_REG
urem32 dst, src
9C
/BPF_MOD32_REG
/mod32 dst, src
76
/01110110
BPF_UREM64_IMM
urem64 dst, imm
97
/BPF_MOD64_IMM
/mod64 dst, imm
7E
/01111110
BPF_UREM64_REG
urem64 dst, src
9F
/BPF_MOD64_REG
/mod64 dst, src
86
/10000110
BPF_LMUL32_IMM
lmul32 dst, imm
24
/BPF_MUL32_IMM
/mul32 dst, imm
8E
/10001110
BPF_LMUL32_REG
lmul32 dst, src
2C
/BPF_MUL32_REG
/mul32 dst, src
96
/10010110
BPF_LMUL64_IMM
lmul64 dst, imm
27
/BPF_MUL64_IMM
/mul64 dst, imm
9E
/10011110
BPF_LMUL64_REG
lmul64 dst, src
2F
/BPF_MUL64_REG
/mul64 dst, src
A6
/10100110
AE
/10101110
B6
/10110110
BPF_SHMUL64_IMM
shmul64 dst, imm
BE
/10111110
BPF_SHMUL64_REG
shmul64 dst, src
C6
/11000110
BPF_SDIV32_IMM
sdiv32 dst, imm
CE
/11001110
BPF_SDIV32_REG
sdiv32 dst, src
D6
/11010110
BPF_SDIV64_IMM
sdiv64 dst, imm
DE
/11011110
BPF_SDIV64_REG
sdiv64 dst, src
E6
/11100110
BPF_SREM32_IMM
srem32 dst, imm
EE
/11101110
BPF_SREM32_REG
srem32 dst, src
F6
/11110110
BPF_SREM64_IMM
srem64 dst, imm
FE
/11111110
BPF_SREM64_REG
srem64 dst, src
In the LLVM backend, the instruction info needs to be adjusted here:
https://github.com/solana-labs/llvm-project/blob/7b8db05b564faffb522434b73b7082662171f94a/llvm/lib/Target/SBF/SBFInstrInfo.td#L311