Initial support for STM32 L5 & U5 devices

(References: #1005 #1096 #1247)

config/chips/L5x5.chip

@@ -0,0 +1,14 @@
+# Chip-ID file for STM32L5x2xx device
+#
+dev_type STM32L5x2xx
+ref_manual_id 0438
+chip_id 0x472                // STM32_CHIPID_L5x2xx
+flash_type L5_U5
+flash_size_reg 0x0bfa05e0
+flash_pagesize 0x1000        // 4 KB
+sram_size 0x40000            // 256 KB
+bootrom_base 0x0bf90000
+bootrom_size 0x8000          // 32 KB
+option_base 0x0
+option_size 0x0
+flags dualbank

config/chips/U5x5.chip.txt → config/chips/U5x5.chip

@@ -2,14 +2,13 @@
 #
 dev_type STM32U5x5
 ref_manual_id 0456
-chip_id 0x0                  // (temporary setting only!)
-flash_type 0                 // (temporary setting only!)
+chip_id 0x482                // STM32_CHIPID_U5x5
+flash_type L5_U5
 flash_size_reg 0x0bfa07a0
-flash_pagesize 0x2000        // 8 KB
+flash_pagesize 0x200000      // 2048 KB
 sram_size 0xc4800            // 786 KB
 bootrom_base 0x0bf90000
-bootrom_size 0x8000          // 32 KB
+bootrom_size 0x10000         // 64 KB
 option_base 0x0
 option_size 0x0
 flags none
-

inc/stm32.h

@@ -117,8 +117,10 @@ enum stm32_chipids {
     STM32_CHIPID_G4_CAT3          = 0x469,
     STM32_CHIPID_L4Rx             = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */
     STM32_CHIPID_L4PX             = 0x471, /* RM0432, p.2247 */
+    STM32_CHIPID_L5x2xx           = 0x472, /* RM0438, p.2157 */
     STM32_CHIPID_G4_CAT4          = 0x479,
     STM32_CHIPID_H7Ax             = 0x480, /* RM0455, p.2863 */
+    STM32_CHIPID_U5x5             = 0x482, /* RM0456, p.2991 */
     STM32_CHIPID_H72x             = 0x483, /* RM0468, p.3199 */
     STM32_CHIPID_WB55             = 0x495,
     STM32_CHIPID_WLE              = 0x497,
@@ -196,10 +198,16 @@ enum stm32_chipids {
 #define STM32L1_RCC_AHBENR 0x4002381C
 #define STM32L1_RCC_DMAEN 0x30000000 // DMA2EN | DMA1EN
 
+#define STM32L5_RCC_AHB1ENR 0x40021048                  // RM0438, p. 91,377
+#define STM32L5_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN // RM0438, p. 378
+
 #define STM32H7_RCC_AHB1ENR 0x58024538
 #define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN
 
 #define STM32WB_RCC_AHB1ENR 0x58000048
 #define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN
 
+#define STM32L5_PWR_CR1 0x40007000                      // RM0438, p. 93,324
+#define STM32L5_PWR_CR1_VOS 8
+
 #endif // STM32_H

inc/stm32flash.h

@@ -72,7 +72,7 @@
 #define FLASH_L1_FPRG 10
 #define FLASH_L1_PROG 3
 
-// Flash registers common to STM32G0 and STM32G4 series.
+// Flash registers common to STM32G0 and STM32G4 series (RM0440, p. 146)
 #define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000)
 #define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00)
 #define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08)
@@ -207,6 +207,43 @@
 
 #define STM32L4_FLASH_OPTR_DUALBANK 21
 
+// Flash registers common to STM32L5 series (RM0438, p. 241)
+#define STM32L5_FLASH_REGS_ADDR ((uint32_t)0x40022000)
+#define STM32L5_FLASH_ACR (STM32L5_FLASH_REGS_ADDR + 0x00)
+#define STM32L5_FLASH_NSKEYR (STM32L5_FLASH_REGS_ADDR + 0x08)
+#define STM32L5_FLASH_OPTKEYR (STM32L5_FLASH_REGS_ADDR + 0x10)
+#define STM32L5_FLASH_NSSR (STM32L5_FLASH_REGS_ADDR + 0x20)
+#define STM32L5_FLASH_NSCR (STM32L5_FLASH_REGS_ADDR + 0x28)
+#define STM32L5_FLASH_ECCR (STM32L5_FLASH_REGS_ADDR + 0x30)
+#define STM32L5_FLASH_OPTR (STM32L5_FLASH_REGS_ADDR + 0x40)
+
+// FLASH_NSCR (RM0438, p. 242)
+#define STM32L5_FLASH_NSCR_NSPG 0        /* Program */
+#define STM32L5_FLASH_NSCR_NSPER 1       /* Page erase */
+#define STM32L5_FLASH_NSCR_NSMER1 2      /* Bank 1 erase */
+#define STM32L5_FLASH_NSCR_NSPNB 3       /* Page number (7 bits) */
+#define STM32L5_FLASH_NSCR_NSBKER 11     /* Bank select for page erase */
+#define STM32L5_FLASH_NSCR_NSMER2 15     /* Bank 2 erase */
+#define STM32L5_FLASH_NSCR_NSSTRT 16     /* Start command */
+#define STM32L5_FLASH_NSCR_NSOPTSTRT 17  /* Start writing option bytes */
+#define STM32L5_FLASH_NSCR_NSEOPIE 24
+#define STM32L5_FLASH_NSCR_NSERRIE 25
+#define STM32L5_FLASH_NSCR_OBL_LAUNCH 27 /* Option bytes reload */
+#define STM32L5_FLASH_NSCR_OPTLOCK 30    /* Lock option bytes */
+#define STM32L5_FLASH_NSCR_NSLOCK 31     /* Lock control register */
+
+// FLASH_NSSR (RM0438, p. 241)
+#define STM32L5_FLASH_NSSR_NSEOP 0       /* End of Operation */
+#define STM32L5_FLASH_NSSR_NSOPERR 1
+#define STM32L5_FLASH_NSSR_NSPROGERR 3
+#define STM32L5_FLASH_NSSR_NSWRPERR 4
+#define STM32L5_FLASH_NSSR_NSPGAERR 5
+#define STM32L5_FLASH_NSSR_NSSIZERR 6
+#define STM32L5_FLASH_NSSR_NSPGSERR 7
+#define STM32L5_FLASH_NSSR_OPTWERR 12
+#define STM32L5_FLASH_NSSR_BSY 16        /* Busy */
+#define STM32L5_FLASH_NSSR_ERROR_MASK (0x20fa)
+
 // STM32L0x flash register base and offsets RM0090 - DM00031020.pdf
 #define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000)
 

src/st-flash/flash.c

@@ -254,6 +254,7 @@ int main(int ac, char** av) {
 
     if (o.reset) {
         stlink_reset(sl, RESET_AUTO);
+        stlink_run(sl, RUN_NORMAL);
     }
 
     err = 0; // success