Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Improvements for Chip_ID read #1120

Merged
merged 2 commits into from
Apr 2, 2021
Merged

Improvements for Chip_ID read #1120

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
ee2c9f5
Core ID reading rework
Ant-ON Mar 23, 2021
36434d5
Added addition check of connected target
Ant-ON Mar 27, 2021
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Jump to
Jump to file
Failed to load files.
Diff view
Diff view
7 changes: 4 additions & 3 deletions inc/stm32.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -8,9 +8,10 @@
#define STM32_H

/* Cortex core ids */
#define STM32VL_CORE_ID 0x1ba01477
#define STM32F7_CORE_ID 0x5ba02477
#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 JTAG ID Code (RM0433 pg3065)
#define STM32VL_CORE_ID 0x1ba01477
#define STM32F7_CORE_ID 0x5ba02477
#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 SWD ID Code
#define STM32H7_CORE_ID_JTAG 0x6ba00477 // STM32H7 JTAG ID Code (RM0433 pg3065)

/* Constant STM32 memory map figures */
#define STM32_FLASH_BASE ((uint32_t)0x08000000)
Expand Down
85 changes: 48 additions & 37 deletions src/common.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1220,36 +1220,65 @@ int stlink_core_id(stlink_t *sl) {
// do not call this procedure directly.
int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) {
int ret;
cortex_m3_cpuid_t cpu_id;

uint32_t cpu_id;
*chip_id = 0;
ret = -1;
// Read the CPU ID to determine where to read the core id
if (stlink_cpu_id(sl, &cpu_id) ||
cpu_id.implementer_id != STLINK_REG_CMx_CPUID_IMPL_ARM) {
ELOG("Can not connect to target. Please use \'connect under reset\' and try again\n");
return -1;
}

// Read the CPU ID to determine where to read the core id from
if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &cpu_id))
cpu_id = 0;
/*
* the chip_id register in the reference manual have
* DBGMCU_IDCODE / DBG_IDCODE name
*
*/

// If the chip is an H7, read the chipid from the new address
if (sl->core_id == STM32H7_CORE_ID && cpu_id == STLINK_REG_CMx_CPUID_CM7) {
if ((sl->core_id == STM32H7_CORE_ID ||
sl->core_id == STM32H7_CORE_ID_JTAG) &&
cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) {
// STM32H7 chipid in 0x5c001000 (RM0433 pg3189)
ret = stlink_read_debug32(sl, 0x5c001000, chip_id);
}

if (*chip_id == 0) {
} else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0) {
// STM32F0 (RM0091, pg914; RM0360, pg713)
// STM32L0 (RM0377, pg813; RM0367, pg915; RM0376, pg917)
// STM32G0 (RM0444, pg1367)
ret = stlink_read_debug32(sl, 0x40015800, chip_id);
} else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM33) {
// STM32L5 (RM0438, pg2157)
ret = stlink_read_debug32(sl, 0xE0044000, chip_id);
} else /* СM3, СM4, CM7 */ {
// default chipid address

// STM32F1 (RM0008, pg1087; RM0041, pg681)
// STM32F2 (RM0033, pg1326)
// STM32F3 (RM0316, pg1095; RM0313, pg874)
// STM32F7 (RM0385, pg1676; RM0410, pg1912)
// STM32L1 (RM0038, pg861)
// STM32L4 (RM0351, pg1840; RM0394, pg1560)
// STM32G4 (RM0440, pg2086)
// STM32WB (RM0434, pg1406)
ret = stlink_read_debug32(sl, 0xE0042000, chip_id);
}

if (*chip_id == 0) {
// Try Corex M0 DBGMCU_IDCODE register address
ret = stlink_read_debug32(sl, 0x40015800, chip_id);
if (ret || !(*chip_id)) {
*chip_id = 0;
ELOG("Could not find chip id!\n");
} else {
*chip_id = (*chip_id) & 0xfff;

// Fix chip_id for F4 rev A errata, read CPU ID, as CoreID is the same for F2/F4
if (*chip_id == 0x411 && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM4) {
*chip_id = 0x413;
}
}

return(ret);
}

/**
* Cortex m3 tech ref manual, CPUID register description
* Cortex M tech ref manual, CPUID register description
* @param sl stlink context
* @param cpuid pointer to the result object
*/
Expand Down Expand Up @@ -1282,26 +1311,16 @@ int stlink_load_device_params(stlink_t *sl) {
DLOG("Loading device parameters....\n");
const struct stlink_chipid_params *params = NULL;
stlink_core_id(sl);
uint32_t chip_id = 0;
uint32_t flash_size;

stlink_chip_id(sl, &chip_id);
sl->chip_id = chip_id & 0xfff;

// Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4
if (sl->chip_id == 0x411) {
uint32_t cpuid;
stlink_read_debug32(sl, 0xE000ED00, &cpuid);

if ((cpuid & 0xfff0) == 0xc240) {
sl->chip_id = 0x413;
}
if (stlink_chip_id(sl, &sl->chip_id)) {
return(-1);
}

params = stlink_chipid_get_params(sl->chip_id);

if (params == NULL) {
WLOG("unknown chip id! %#x\n", chip_id);
WLOG("unknown chip id! %#x\n", sl->chip_id);
return(-1);
}

Expand Down Expand Up @@ -1367,19 +1386,11 @@ int stlink_load_device_params(stlink_t *sl) {
sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK;
}

#if 0
// Old code -- REW
ILOG("Device connected is: %s, id %#x\n", params->description, chip_id);
// TODO: make note of variable page size here.....
ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %u bytes\n",
sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024,
(unsigned int)sl->flash_pgsz);
#else
ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n",
params->description, (unsigned)(sl->sram_size / 1024), (unsigned)(sl->flash_size / 1024),
(sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) : (unsigned)(sl->flash_pgsz / 1024),
(sl->flash_pgsz < 1024) ? "byte" : "KiB");
#endif

return(0);
}

Expand Down
9 changes: 6 additions & 3 deletions src/stlink-lib/reg.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3,9 +3,12 @@

#define STLINK_REG_CM3_CPUID 0xE000ED00

#define STLINK_REG_CMx_CPUID_CM0 0x410CC200
#define STLINK_REG_CMx_CPUID_CM3 0x412FC230
#define STLINK_REG_CMx_CPUID_CM7 0x411FC272
#define STLINK_REG_CMx_CPUID_PARTNO_CM0 0xC20
#define STLINK_REG_CMx_CPUID_PARTNO_CM3 0xC23
#define STLINK_REG_CMx_CPUID_PARTNO_CM4 0xC24
#define STLINK_REG_CMx_CPUID_PARTNO_CM7 0xC27
#define STLINK_REG_CMx_CPUID_PARTNO_CM33 0xD21
#define STLINK_REG_CMx_CPUID_IMPL_ARM 0x41


#define STLINK_REG_CM3_FP_CTRL 0xE0002000 // Flash Patch Control Register
Expand Down