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Allow pin modes OpenDrain and PushPull for SPI output pins #226

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Mar 31, 2023
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2 changes: 2 additions & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@ forget to update the links at the bottom of the changelog as well.-->

### Additions

- SPI: Allow output pins of mode `PushPull` and `OpenDrain` ([#226])
- Enable TIM2 outputs on `PA5`, `PA15`, `PB3` for all devices in the L0 family (previously only 0x2
and 0x3) ([#224])
- Enable SPI2 on subset of stm32l0x1 devices ([#221])
Expand Down Expand Up @@ -186,6 +187,7 @@ _Not yet tracked in this changelog._

<!-- Links to pull requests and issues. -->

[#226]: https://github.com/stm32-rs/stm32l0xx-hal/pull/226
[#224]: https://github.com/stm32-rs/stm32l0xx-hal/pull/224
[#221]: https://github.com/stm32-rs/stm32l0xx-hal/pull/221
[#220]: https://github.com/stm32-rs/stm32l0xx-hal/pull/218
Expand Down
9 changes: 2 additions & 7 deletions src/rcc.rs
Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@ pub enum ClockSrc {
///
/// These ranges control the frequency of the MSI. Internally, these ranges map
/// to the `MSIRANGE` bits in the `RCC_ICSCR` register.
#[derive(Clone, Copy)]
#[derive(Clone, Copy, Default)]
pub enum MSIRange {
/// Around 65.536 kHz
Range0 = 0,
Expand All @@ -35,17 +35,12 @@ pub enum MSIRange {
/// Around 1.048 MHz
Range4 = 4,
/// Around 2.097 MHz (reset value)
#[default]
Range5 = 5,
/// Around 4.194 MHz
Range6 = 6,
}

impl Default for MSIRange {
fn default() -> MSIRange {
MSIRange::Range5
}
}

/// HSI16 divider
#[derive(Clone, Copy)]
pub enum HSI16Div {
Expand Down
38 changes: 31 additions & 7 deletions src/spi.rs
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ use crate::dma::{self, Buffer};
use crate::gpio::gpioa::*;
use crate::gpio::gpiob::*;

use crate::gpio::{AltMode, Analog};
use crate::gpio::{AltMode, Analog, OpenDrain, Output, PushPull};
use crate::hal;
use crate::pac::SPI1;
#[cfg(any(
Expand Down Expand Up @@ -119,8 +119,12 @@ pins! {
SPI1:
SCK: [
[NoSck, None],
[PA5<Analog>, AltMode::AF0],
[PA5<Output<OpenDrain>>, AltMode::AF0],
[PA5<Output<PushPull>>, AltMode::AF0],
[PB3<Analog>, AltMode::AF0],
[PA5<Analog>, AltMode::AF0]
[PB3<Output<OpenDrain>>, AltMode::AF0],
[PB3<Output<PushPull>>, AltMode::AF0]
]
MISO: [
[NoMiso, None],
Expand All @@ -131,8 +135,14 @@ pins! {
MOSI: [
[NoMosi, None],
[PA7<Analog>, AltMode::AF0],
[PA7<Output<OpenDrain>>, AltMode::AF0],
[PA7<Output<PushPull>>, AltMode::AF0],
[PA12<Analog>, AltMode::AF0],
[PB5<Analog>, AltMode::AF0]
[PA12<Output<OpenDrain>>, AltMode::AF0],
[PA12<Output<PushPull>>, AltMode::AF0],
[PB5<Analog>, AltMode::AF0],
[PB5<Output<OpenDrain>>, AltMode::AF0],
[PB5<Output<PushPull>>, AltMode::AF0]
]
}

Expand All @@ -146,15 +156,19 @@ pins! {
SPI2:
SCK: [
[NoSck, None],
[PB13<Analog>, AltMode::AF0]
[PB13<Analog>, AltMode::AF0],
[PB13<Output<OpenDrain>>, AltMode::AF0],
[PB13<Output<PushPull>>, AltMode::AF0]
]
MISO: [
[NoMiso, None],
[PB14<Analog>, AltMode::AF0]
]
MOSI: [
[NoMosi, None],
[PB15<Analog>, AltMode::AF0]
[PB15<Analog>, AltMode::AF0],
[PB15<Output<OpenDrain>>, AltMode::AF0],
[PB15<Output<PushPull>>, AltMode::AF0]
]
}

Expand All @@ -164,7 +178,11 @@ pins! {
SCK: [
[NoSck, None],
[PA5<Analog>, AltMode::AF0],
[PB3<Analog>, AltMode::AF0]
[PA5<Output<OpenDrain>>, AltMode::AF0],
[PA5<Output<PushPull>>, AltMode::AF0],
[PB3<Analog>, AltMode::AF0],
[PB3<Output<OpenDrain>>, AltMode::AF0],
[PB3<Output<PushPull>>, AltMode::AF0]
]
MISO: [
[NoMiso, None],
Expand All @@ -175,8 +193,14 @@ pins! {
MOSI: [
[NoMosi, None],
[PA7<Analog>, AltMode::AF0],
[PA7<Output<OpenDrain>>, AltMode::AF0],
[PA7<Output<PushPull>>, AltMode::AF0],
[PA12<Analog>, AltMode::AF0],
[PB5<Analog>, AltMode::AF0]
[PA12<Output<OpenDrain>>, AltMode::AF0],
[PA12<Output<PushPull>>, AltMode::AF0],
[PB5<Analog>, AltMode::AF0],
[PB5<Output<OpenDrain>>, AltMode::AF0],
[PB5<Output<PushPull>>, AltMode::AF0]
]
}

Expand Down