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This PR removes the
data_width_c
package constant, which defines the "native data width" of the whole NEORV32 processor.This is very a first step towards supporting the RISC-V 64-bit ISA
rv64
.The SoC (so all memories and peripherals) will be 32-bit only. The CPU core itself will provide a new configuration generic
XLEN
that allows to specify the core's native data width (32-bit or 64-bit). This generic is not yet available!This is still very early stuff and highly experimental! Full RV64 support will/might be added somewhere in the future.