Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[rtl] XLEN cleanup #417

Merged
merged 9 commits into from
Sep 23, 2022
Merged

[rtl] XLEN cleanup #417

merged 9 commits into from
Sep 23, 2022

Conversation

stnolting
Copy link
Owner

@stnolting stnolting commented Sep 23, 2022

This PR removes the data_width_c package constant, which defines the "native data width" of the whole NEORV32 processor.

This is very a first step towards supporting the RISC-V 64-bit ISA rv64.

The SoC (so all memories and peripherals) will be 32-bit only. The CPU core itself will provide a new configuration generic XLEN that allows to specify the core's native data width (32-bit or 64-bit). This generic is not yet available!

This is still very early stuff and highly experimental! Full RV64 support will/might be added somewhere in the future.

@stnolting stnolting added enhancement New feature or request HW Hardware-related experimental Experimental feature labels Sep 23, 2022
@stnolting stnolting self-assigned this Sep 23, 2022
@stnolting stnolting removed the experimental Experimental feature label Sep 23, 2022
@stnolting stnolting marked this pull request as ready for review September 23, 2022 19:31
@stnolting stnolting merged commit d6d94c6 into main Sep 23, 2022
@stnolting stnolting deleted the xlen_cleanup branch September 23, 2022 21:46
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
enhancement New feature or request HW Hardware-related
Projects
None yet
Development

Successfully merging this pull request may close these issues.

1 participant