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[rtl] XLEN cleanup #417

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merged 9 commits into from
Sep 23, 2022
Merged

[rtl] XLEN cleanup #417

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67d0d55
[rtl] make SoC 32-bit wide only
stnolting Sep 23, 2022
233e4f6
[rtl] SoC data width is fixed to 32-bit
stnolting Sep 23, 2022
9586735
[CPU] ALU: add support for XLEN
stnolting Sep 23, 2022
d4233ee
[CPU] BUS: add support for XLEN/rv64
stnolting Sep 23, 2022
0ec1cf5
[CPU] REGFILE: add support for XLEN/rv64
stnolting Sep 23, 2022
38c9547
[CPU] CTRL: add support for XLEN
stnolting Sep 23, 2022
4c2077b
[CPU] add intial support for XLEN
stnolting Sep 23, 2022
d1c0aa9
[CHANGELOG] add v1.7.6.10
stnolting Sep 23, 2022
b07a324
[CPU} XLEN generic is not yet available
stnolting Sep 23, 2022
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1 change: 1 addition & 0 deletions CHANGELOG.md
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Expand Up @@ -32,6 +32,7 @@ mimpid = 0x01040312 => 01.04.03.12 => Version 01.04.03.12 => v1.4.3.12

| Date (*dd.mm.yyyy*) | Version | Comment |
|:-------------------:|:-------:|:--------|
| 23.09.2022 | 1.7.6.10 | cleanup native data path size (remove `data_width_c` package constant); initial preparations to **support RV64 ISA extension** somewhere in the future; [#417](https://github.com/stnolting/neorv32/pull/417) |
| 18.09.2022 | 1.7.6.9 | :bug: fixed instruction decoding collision in **`B` ISA extensions** - `B` extension is now fully operational and verified (see [neorv32-riscof](https://github.com/stnolting/neorv32-riscof))! [#413](https://github.com/stnolting/neorv32/pull/413) |
| 13.09.2022 | 1.7.6.8 | :bug: bug fix: clearing `mie`'s FIRQ bits did not clear the according _pending_ FIRQs; [#411](https://github.com/stnolting/neorv32/pull/411) |
| 12.09.2022 | 1.7.6.7 | minor rtl edits and cleanups; [#410](https://github.com/stnolting/neorv32/pull/410) |
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18 changes: 9 additions & 9 deletions rtl/core/neorv32_busswitch.vhd
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Expand Up @@ -54,9 +54,9 @@ entity neorv32_busswitch is
-- controller interface a --
ca_bus_priv_i : in std_ulogic; -- current privilege level
ca_bus_cached_i : in std_ulogic; -- set if cached transfer
ca_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
ca_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
ca_bus_addr_i : in std_ulogic_vector(31 downto 0); -- bus access address
ca_bus_rdata_o : out std_ulogic_vector(31 downto 0); -- bus read data
ca_bus_wdata_i : in std_ulogic_vector(31 downto 0); -- bus write data
ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
ca_bus_we_i : in std_ulogic; -- write enable
ca_bus_re_i : in std_ulogic; -- read enable
Expand All @@ -65,9 +65,9 @@ entity neorv32_busswitch is
-- controller interface b --
cb_bus_priv_i : in std_ulogic; -- current privilege level
cb_bus_cached_i : in std_ulogic; -- set if cached transfer
cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
cb_bus_addr_i : in std_ulogic_vector(31 downto 0); -- bus access address
cb_bus_rdata_o : out std_ulogic_vector(31 downto 0); -- bus read data
cb_bus_wdata_i : in std_ulogic_vector(31 downto 0); -- bus write data
cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
cb_bus_we_i : in std_ulogic; -- write enable
cb_bus_re_i : in std_ulogic; -- read enable
Expand All @@ -77,9 +77,9 @@ entity neorv32_busswitch is
p_bus_priv_o : out std_ulogic; -- current privilege level
p_bus_cached_o : out std_ulogic; -- set if cached transfer
p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
p_bus_addr_o : out std_ulogic_vector(31 downto 0); -- bus access address
p_bus_rdata_i : in std_ulogic_vector(31 downto 0); -- bus read data
p_bus_wdata_o : out std_ulogic_vector(31 downto 0); -- bus write data
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
p_bus_we_o : out std_ulogic; -- write enable
p_bus_re_o : out std_ulogic; -- read enable
Expand Down
84 changes: 45 additions & 39 deletions rtl/core/neorv32_cpu.vhd
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Expand Up @@ -82,18 +82,18 @@ entity neorv32_cpu is
sleep_o : out std_ulogic; -- cpu is in sleep mode when set
debug_o : out std_ulogic; -- cpu is in debug mode when set
-- instruction bus interface --
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
i_bus_addr_o : out std_ulogic_vector(31 downto 0); -- bus access address
i_bus_rdata_i : in std_ulogic_vector(31 downto 0); -- bus read data
i_bus_re_o : out std_ulogic; -- read request
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
i_bus_err_i : in std_ulogic; -- bus transfer error
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
i_bus_priv_o : out std_ulogic; -- current effective privilege level
-- data bus interface --
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
d_bus_addr_o : out std_ulogic_vector(31 downto 0); -- bus access address
d_bus_rdata_i : in std_ulogic_vector(31 downto 0); -- bus read data
d_bus_wdata_o : out std_ulogic_vector(31 downto 0); -- bus write data
d_bus_ben_o : out std_ulogic_vector(3 downto 0); -- byte enable
d_bus_we_o : out std_ulogic; -- write request
d_bus_re_o : out std_ulogic; -- read request
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
Expand All @@ -115,25 +115,30 @@ end neorv32_cpu;

architecture neorv32_cpu_rtl of neorv32_cpu is

-- RV64: WORK IN PROGRESS -----------------------------------------------------------------------
-- not available as CPU generic as rv64 ISA extension is not (fully) supported yet
constant XLEN : natural := 32; -- data path width
-- ----------------------------------------------------------------------------------------------

-- local signals --
signal ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
signal imm : std_ulogic_vector(data_width_c-1 downto 0); -- immediate
signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu address result
signal imm : std_ulogic_vector(XLEN-1 downto 0); -- immediate
signal rs1, rs2 : std_ulogic_vector(XLEN-1 downto 0); -- source registers
signal alu_res : std_ulogic_vector(XLEN-1 downto 0); -- alu result
signal alu_add : std_ulogic_vector(XLEN-1 downto 0); -- alu address result
signal alu_cmp : std_ulogic_vector(1 downto 0); -- comparator result
signal mem_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
signal mem_rdata : std_ulogic_vector(XLEN-1 downto 0); -- memory read data
signal alu_idone : std_ulogic; -- iterative alu operation done
signal bus_d_wait : std_ulogic; -- wait for current bus data access
signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
signal mar : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
signal csr_rdata : std_ulogic_vector(XLEN-1 downto 0); -- csr read data
signal mar : std_ulogic_vector(XLEN-1 downto 0); -- current memory address register
signal ma_load : std_ulogic; -- misaligned load data address
signal ma_store : std_ulogic; -- misaligned store data address
signal be_load : std_ulogic; -- bus error on load data access
signal be_store : std_ulogic; -- bus error on store data access
signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for next executed instruction)
signal fetch_pc : std_ulogic_vector(XLEN-1 downto 0); -- pc for instruction fetch
signal curr_pc : std_ulogic_vector(XLEN-1 downto 0); -- current pc (for current executed instruction)
signal next_pc : std_ulogic_vector(XLEN-1 downto 0); -- next pc (for next executed instruction)
signal fpu_flags : std_ulogic_vector(4 downto 0); -- FPU exception flags
signal i_pmp_fault : std_ulogic; -- instruction fetch PMP fault

Expand All @@ -143,39 +148,36 @@ architecture neorv32_cpu_rtl of neorv32_cpu is

begin

-- CPU ISA Configuration ---------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
assert false report
"NEORV32 CPU CONFIG NOTE: Core ISA ('MARCH') = " &
cond_sel_string_f(boolean(data_width_c = 32), "RV32", "RV64") &
cond_sel_string_f(CPU_EXTENSION_RISCV_E, "E", "I") &
cond_sel_string_f(CPU_EXTENSION_RISCV_M, "M", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_C, "C", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_B, "B", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_U, "U", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zicsr, "_Zicsr", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zicntr, "_Zicntr", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zihpm, "_Zihpm", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zifencei, "_Zifencei", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zfinx, "_Zfinx", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zmmul, "_Zmmul", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zxcfu, "_Zxcfu", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_DEBUG, "_<DebugMode>", "") &
""
severity note;


-- Sanity Checks --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- say hello --
assert false report "The NEORV32 RISC-V Processor - github.com/stnolting/neorv32" severity note;

-- CPU ISA configuration --
assert false report
"NEORV32 CPU CONFIG NOTE: Core ISA ('MARCH') = RV32" &
cond_sel_string_f(CPU_EXTENSION_RISCV_E, "E", "I") &
cond_sel_string_f(CPU_EXTENSION_RISCV_M, "M", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_C, "C", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_B, "B", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_U, "U", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zicsr, "_Zicsr", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zicntr, "_Zicntr", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zihpm, "_Zihpm", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zifencei, "_Zifencei", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zfinx, "_Zfinx", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zmmul, "_Zmmul", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zxcfu, "_Zxcfu", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_DEBUG, "_<DebugMode>", "") &
""
severity note;

-- simulation notifier --
assert not (is_simulation_c = true) report "NEORV32 CPU WARNING! Assuming this is a simulation." severity warning;
assert not (is_simulation_c = false) report "NEORV32 CPU NOTE: Assuming this is real hardware." severity note;

-- native data width check --
assert not ((data_width_c /= 32) and (data_width_c /= 64)) report "NEORV32 CPU CONFIG ERROR! Invalid <data_width_c> data path width (has to be 32 or 64)." severity error;
assert not (XLEN /= 32) report "NEORV32 CPU CONFIG ERROR! <XLEN> native data path width has to be 32 (bit)." severity error;

-- CPU boot address --
assert not (CPU_BOOT_ADDR(1 downto 0) /= "00") report "NEORV32 CPU CONFIG ERROR! <CPU_BOOT_ADDR> has to be 32-bit aligned." severity error;
Expand Down Expand Up @@ -223,6 +225,7 @@ begin
neorv32_cpu_control_inst: neorv32_cpu_control
generic map (
-- General --
XLEN => XLEN, -- data path width
HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id
CPU_BOOT_ADDR => CPU_BOOT_ADDR, -- cpu boot address
CPU_DEBUG_ADDR => CPU_DEBUG_ADDR, -- cpu debug mode start address
Expand Down Expand Up @@ -312,6 +315,7 @@ begin
-- -------------------------------------------------------------------------------------------
neorv32_cpu_regfile_inst: neorv32_cpu_regfile
generic map (
XLEN => XLEN, -- data path width
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E -- implement embedded RF extension?
)
port map (
Expand All @@ -333,6 +337,7 @@ begin
-- -------------------------------------------------------------------------------------------
neorv32_cpu_alu_inst: neorv32_cpu_alu
generic map (
XLEN => XLEN, -- data path width
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit-manipulation extension?
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension?
Expand Down Expand Up @@ -367,6 +372,7 @@ begin
-- -------------------------------------------------------------------------------------------
neorv32_cpu_bus_inst: neorv32_cpu_bus
generic map (
XLEN => XLEN, -- data path width
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..16)
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
)
Expand Down
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