Control register map

##Summarise control register set used in RTL design. Table below doesn't list all the control registers that are specified in SD specification. It contains registers are used by controller. The controller hasn't registers related to the features that are not implemented in current version. For example: Buffer Data Port, SDMA System Address registers which are not used cause they related to previous controller version or such as Maximum Current Capabilities and Shared Bus Control registers which are related to features hasn't been implemented in current version. These registers are not considered here but they have reserved in RTL design for the future use.

Note: The page is focused on a basic information concerning registers and their fields. The information is combined from the SD and eMMC standard specifications. Some descriptions have been reduced since there is no necessary to duplicate whole content of specifications. If you need more specific and extended information of certain register you may found it in documents listed in reference.

Standard register name	offset	Width, [bits]	Register name in RTL design, [module\reg]
Argument2	0x00	32	sd_emmc_controller_S00_AXI\ slv_reg0
Block size	0x04	16	sd_emmc_controller_S00_AXI\ slv_reg1
Block count	0x06	16	sd_emmc_controller_S00_AXI\ slv_reg1
Argument1	0x08	32	sd_emmc_controller_S00_AXI\ slv_reg2
Transfer mode	0x0c	16	sd_emmc_controller_S00_AXI\ slv_reg3
Command	0x0e	16	sd_emmc_controller_S00_AXI\ slv_reg3
Response0	0x10	32	sd_cmd_master\ response_i[31:0]
Response1	0x14	32	sd_cmd_master\ response_i[63:32]
Response2	0x18	32	sd_cmd_master\ response_i[95:64]
Response3	0x1c	32	sd_cmd_master\ response_i[119:96]
Present State	0x24	32	sd_emmc_controller_S00_AXI\ slv_reg9
Host control1	0x28	8	sd_emmc_controller_S00_AXI\ slv_reg10
Clock control	0x2c	16	sd_emmc_controller_S00_AXI\ slv_reg11
Timeout control	0x2e	8	sd_emmc_controller_S00_AXI\ slv_reg11
Software reset	0x2f	8	sd_emmc_controller_S00_AXI\ slv_reg11
Normal Interrupt status	0x30	16	sd_emmc_controller_S00_AXI\ slv_reg12
Error Interrupt status	0x32	16	sd_emmc_controller_S00_AXI\ slv_reg12
Normal Interrupt status enable	0x34	16	sd_emmc_controller_S00_AXI\ slv_reg13
Error Interrupt status enable	0x36	16	sd_emmc_controller_S00_AXI\ slv_reg13
Normal Interrupt signal enable	0x38	16	sd_emmc_controller_S00_AXI\ slv_reg14
Error Interrupt signal enable	0x3a	16	sd_emmc_controller_S00_AXI\ slv_reg14
Auto CMD Error Status	0x3c	16	sd_emmc_controller_S00_AXI\ ACMDErrorStatus
Capabilities	0x40	32	sd_emmc_controller_S00_AXI\ reg_data_out
ADMA System Address	0x58	32	sd_emmc_controller_S00_AXI\ slv_reg22
Host Control version	0xfe	16	sd_emmc_controller_S00_AXI\ reg_data_out

##Configuration register types Configuration register fields are assigned one of the attributes described below:

Register Attribute	Description
RO	Read only register: Register bits are read-only and cannot be altered by software or any reset operation.
ROC	Read-only status: These bits are initialized to zero at reset. Writes to these bits are ignored. Writes to these bits are ignored.
RW	Read-Write register: Register bits are read-write and may be either set or cleared by software to the desired state.
RW1C	Read-only status, Write-1-to-clear status: Register bits indicate status when read, a set bit indicating a status event may be cleared by writing a 1. Writing a 0 to RW1C bits has no effect.
RWAC	Read-Write, automatic clear register: The Host Driver requests a Host Controller operation by setting the bit. The Host Controllers shall clear the bit automatically when the operation of complete. Writing a 0 to RWAC bits has no effect.
HwInit	Hardware Initialised: Register bits are initialised by firmware or hardware mechanisms such as pin strapping or serial EEPROM. Bits are read-only after initialisation, and writes to these bits are ignored.
Rswd	Reserved. These bits are initialized to zero, and writes to them are ignored.
WO	Write-only register. It is not physically implemented register. Rather, it is an address at which registers can be written.

##Detailed register description ###Argument 2 Register (Offset 000h), [RW] This register is used with the Auto CMD23 to set a 32-bit block count value to the argument of the CMD23 while executing Auto CMD23. If Auto CMD23 is used with ADMA, the full 32-bit block count value can be used. If Auto CMD23 is used without ADMA, the available block count value is limited by the Block Count register. 65535 blocks is the maximum value in this case.

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###Block Size Register (Offset 004h) This register is used to configure the number of bytes in a data block.

D15	D14 ----- D12	D11 ----- D00
Rsvd	Host SDMA buffer boundary, [RW]	Transfer block size, [RW]

Host SDMA Buffer Boundary bits-field is not used in current version controller since ADMA used instead of SDMA.

Transfer Block Size register specifies the block size of data transfers for CMD17, CMD18, CMD24, CMD25, and CMD53. Values ranging from 1 up to the maximum buffer size can be set. In case of memory, it shall be set up to 512 bytes.

0800h	2048 Bytes
...	...
0200h	512 Bytes
01FFh	511 Bytes
...	...
0002h	2 Bytes
0001h	1 Bytes
0000h	No data transfer

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###Block Count Register (Offset 006h), [RW] This register is used to configure the number of data blocks.
This register is enabled when Block Count Enable in the Transfer Mode register is set to 1 and is valid only for multiple block transfers. The Host Driver shall set this register to a value between 1 and the maximum block count. The Host Controller decrements the block count after each block transfer and stops when the count reaches zero. Setting the block count to 0 results in no data blocks is transferred.

FFFFh	65535 Blocks
...	...
0002h	2 Bytes
0001h	1 Bytes
0000h	Stop count

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###Argument 1 Register (Offset 008h), [RW] This register contains the SD/eMMC Command Argument.
Command Argument 1. The command argument is specified as bits 39-8 of Command-Format in the Physical Layer Specification.

Description	Start Bit	Transmission Bit	Command Index	Argument	CRC7	End Bit
Bit position	47	46	[45-40]	[39-8]	[7-1]	0
Width (bit)	1	1	6	32	7	1
Value	"0"	"1"	x	x	x	"1"

All commands have a fixed code length of 48 bits. A command always starts with a start bit (always ‘0’), followed by the bit indicating the direction of transmission (host = ‘1’). The next 6 bits indicate the index of the command, this value being interpreted as a binary coded number (between 0 and 63). Some commands need an argument (e.g., an address), that is coded by 32 bits. A value denoted by ‘x’ indicates this variable is dependent on the command. All commands are protected by a CRC. Every command codeword is terminated by the end bit (always ‘1’).

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###Transfer Mode Register (Offset 00Ch) This register is used to control the operation of data transfers. The Host Driver shall set this register before issuing a command which transfers data (Refer to Data Present Select in the Command register), or before issuing a Resume command. The Host Driver shall save the value of this register when the data transfer is suspended (as a result of a Suspend command) and restore it before issuing a Resume command. To prevent data loss, the Host controller shall implement write protection for this register during data transactions. Writes to this register shall be ignored when the Command Inhibit (DAT) in the Present State register is 1.

D15-----D06	D05	D04	D03 ----- D02	D01	D00
Rsvd	Mult/Sing block sel.,[RW]	Data trans dir sel,[RW]	Auto CMD Enable, [RW]	Block Count Enable,[RW]	DMA Enable,[RW]

Mult/Sing block sel bit is set when issuing multiple-block transfer commands using DAT line. For any other commands, this bit shall be set to 0. If this bit is 0, it is not necessary to set the Block Count register.

1	Multiple block
0	Single block

Data trans dir sel bit defines the direction of DAT line data transfers. The bit is set to 1 by the Host Driver to transfer data from the memory card to the SD Host Controller and it is set to 0 for all other commands.

1	Read (Card to Host)
0	Write (Host to Card)

Auto CMD Enable field determines use of auto command functions. There are two methods to stop Multiple-block read and write operation: (1) Auto CMD12 Enable; (2) Auto CMD23 Enable;

00b	Auto Command Disabled
01b	Auto CMD12 Enable
10b	Auto CMD23 Enable
11b	Reserved

Block Count Enable bit is used to enable the Block Count register, which is only relevant for multiple block transfers. When this bit is 0, the Block Count register is disabled, which is useful in executing an infinite transfer. If ADMA2 data transfer is more than 65535 blocks, this bit shall be set to 0. In this case, data transfer length is designated by Descriptor Table.

1	Enable
2	Disable

DMA Enable bit enables DMA functionality. DMA can be enabled only if it is supported as indicated in the Capabilities register. One of the DMA modes can be selected by DMA Select in the Host Control 1 register. If DMA is not supported, this bit is meaningless and shall always read 0. If this bit is set to 1, a DMA operation shall begin when the Host Driver writes to the upper byte of Command register (00Fh).

1	DMA Data transfer
0	No data transfer or Non DMA data transfer

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###Command Register (Offset 00Eh) The Host Driver shall check the Command Inhibit (DAT) bit and Command Inhibit (CMD) bit in the Present State register before writing to this register. Writing to the upper byte of this register triggers SD command generation. The Host Driver has the responsibility to write this register because the Host Controller does not protect for writing when Command Inhibit (CMD) is set.

D15-D14	D13-----D08	D07-D06	D05	D04	D03	D02	D01-D00
Rsvd	Command Index, [RW]	Command Type, [RW]	Data Present Select, [RW]	Command Index Check Ena., [RW]	Command CRC Check Ena., [RW]	Rsvd	Response Type Sel., [RW]

Command Index. These bits shall be set to the command number (CMD0-63, ACMD0-63) that is specified in bits 45-40 of the Command-Format in the Physical Layer Specification and SDIO Card Specification.

Command Type. There are three types of special commands: Suspend, Resume and Abort. These bits shall be set to 00b for all other commands.

11b	Abort	CMD12, CMD52 for writing "I/O Abort" in CCCR
10b	Resume	CMD52 for writing "Function Select" in CCCR
01b	Suspend	CMD52 for writing "Bus Suspend" in CCCR
00b	Normal	Other commands

Data Present Select bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. It is set to 0 for the following:

(1) Commands using only CMD line (ex. CMD52).
(2) Commands with no data transfer but using busy signal on DAT[0] line (R1b or R5b ex. CMD38).
(3) Resume command.
'1' - Data Present;
'0' - No Data Present;

Command Index Check Enable. If this bit is set to 1, the Host Controller shall check the Index field in the response to see if it has the same value as the command index. If it is not, it is reported as a Command Index Error. If this bit is set to 0, the Index field is not checked.
'1' - Enable;
'0' - Disable;

Command CRC Check Enable. If this bit is set to 1, the Host Controller shall check the CRC field in the response. If an error is detected, it is reported as a Command CRC Error. If this bit is set to 0, the CRC field is not checked. The position of CRC field is determined according to the length of the response.
'1' - Enable;
'0' - Disable;

Response Type Select.

00	No Response
01	Response Length 136
10	Response Length 48
11	Response Length 48 check Busy after response

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###Response Register (Offset 010h), [ROC] This register is used to store responses from memory cards.

Offset 010h|D31-----D00| |:---|:---:|:---:| ||Command Response 0-31| Offset 014h|D31-----D00| ||Command Response 32-63| Offset 018h|D31-----D00| ||Command Response 64-95| Offset 01Ch|D31-----D00| ||Command Response 96-127|

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###Present State Register (Offset 024h) The Host Driver can get status of the Host Controller from this 32-bit read only register.

D31-----D25	D24	D23-----D20	D19	D18	D17	D16	D15-----D12	D11	D10	D09	D08	D07-----D04	D03	D02	D01	D00
Rsvd	CMD Line Sig. Lev., [RO]	DAT[3:0] Line Sig. Lev., [RO]	Write Protect Sw. Pin Lev., [RO]	Card Det. Pin. Lev., [RO]	Card state stable, [RO]	Card Ins., [RO]	Rsvd	Buff. Rd. Ena., [ROC]	Buff. Wr. Ena., [ROC]	Rd. Trans. Act., [ROC]	Wr. Trans. Act., [ROC]	Rsvd	Re-Tuning Req., [ROC]	DAT Line Act., [ROC]	Command Inhibit (DAT), [ROC]	Command Inhibit (CMD), [ROC]

CMD Line Signal Level. This status is used to check the CMD line level to recover from errors, and for debugging.

DAT[3:0] Line Signal Level. This status is used to check the DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0].

D23	DAT[3]
D22	DAT[2]
D21	DAT[1]
D20	DAT[0]

Write Protect Switch Pin Level. The Write Protect Switch is supported for memory and combo cards. This bit reflects the WP# pin.
'1' - Write Enabled(WP# = 1);
'0' - Write protected(WP# = 0);

Card Detect Pin Level. This bit reflects the inverse value of the CD# pin. Debouncing is not performed on this bit. This bit may be valid when Card State Stable is set to 1, but it is not guaranteed because of propagation delay. Use of this bit is limited to testing since it must be debounced by software.
'1' - Card Present (CD# = 1);
'0' - No card Present (CD# = 0);

Card State Stable. This bit is used for testing. If it is 0, the Card Detect Pin Level is not stable. If this bit is set to 1, it means the Card Detect Pin Level is stable. No Card state can be detected by this bit is set to 1 and Card Inserted is set to 0. The Software Reset For All in the Software Reset register shall not affect this bit.

Card Inserted. This bit indicates whether a card has been inserted. The Host Controller shall debounce this signal so that the Host Driver will not need to wait for it to stabilize.
'1' - Card Inserted;
'0' - Reset or De-bouncing or No card;

Buffer Read Enable. This status is used for non-DMA read transfers. It is not used in current version of controller.

Buffer Write Enable. This status is used for non-DMA read transfers. It is not used in current version of controller.

Re-Tuning Request. Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data.
'1' - Sampling clock needs re-tuning;
'0' - Fixed or well tuned sampling clock;

DAT Line Active. This bit indicates whether one of the DAT line on SD Bus is in use.
'1' - DAT Line Active;
'0' - DAT Line Inactive;

Command Inhibit (DAT). This status bit is generated if either the DAT Line Active or the Read Transfer Active is set to 1. If this bit is 0, it indicates the Host Controller can issue the next SD/eMMC Command. Commands with busy signal belong to Command Inhibit (DAT) (ex. R1b, R5b type). Changing from 1 to 0 generates a Transfer Complete interrupt in the Normal Interrupt Status register.
'1' - Cannot issue command which uses the DAT line;
'0' - Can issue command which uses the DAT line;

Command Inhibit (CMD). If this bit is 0, it indicates the CMD line is not in use and the Host Controller can issue a SD Command using the CMD line.
'1' - Can not issue command;
'0' - Can issue command using only CMD line;

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###Host Control 1 Register (Offset 028h), [RW]

D07	D06	D05	D04-D03	D02	D01	D00
Card Det. Sig. Sel.	Card Det. Test Lev.	Extended Data Trans. Width	DMA Sel.	High Speed Ena.	Data Trans. Width	LED Control

Card Detect Signal Selection bit selects source for the card detection.
'1' - The Card Detect Test Level is selected (for test purpose);
'0' - CD# is selected (for normal use);

Card Detect Test Level bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not.
'1' - Card Inserted;
'0' - No card;

Extended Data Transfer Width bit controls 8-bit bus width mode for embedded device. Support of this function is indicated in 8-bit Support for Embedded Device in the Capabilities register. If a device supports 8-bit bus mode, this bit may be set to 1. If this bit is 0, bus width is controlled by Data Transfer Width in the Host Control 1 register. This bit is not effective when multiple devices are installed on a bus slot (Slot Type is set to 10b in the Capabilities register). In this case, each device bus width is controlled by Bus Width Preset field in the Shared Bus Control register.
'1' - 8-bit Bus Width;
'0' - Bus Width is Selected by Data Transfer Width;

DMA Select. One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring the Capabilities register. Use of selected DMA is determined by DMA Enable of the Transfer Mode register.

00	SDMA is selected
01	Reserved (New assignment is not allowed)
10	32-bit Address ADMA2 is selected
11	Reserved (will be modified by Version 4.00)

High Speed Enable bit is optional. Before setting this bit, the Host Driver shall check the High Speed Support in the Capabilities register. If this bit is set to 0 (default), the Host Controller outputs CMD line and DAT lines at the falling edge of the SD Clock (up to 25MHz). If this bit is set to 1, the Host Controller outputs CMD line and DAT lines at the rising edge of the SD Clock (up to 50MHz).
'1' - High Speed Mode;
'0' - Normal Speed Mode;

Data Transfer Width bit selects the data width of the Host Controller. The Host Driver shall set it to match the data width of the SD card.
'1' - 4-bit mode;
'0' - 1-bit mode;

LED Control bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue multiple SD commands, this bit can be set during all these transactions. It is not necessary to change for each transaction.
'1' - LED on;
'0' - LED off;

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###Clock Control Register (Offset 02Ch) At the initialization of the Host Controller, the Host Driver shall set the SDCLK Frequency Select according to the Capabilities register.

D15-----D08	D07-D06	D05	D04-D03	D02	D01	D00
SDCLK Frequency Sel., [RW]	Upper bits of SDCLK Freq. Sel., [RW]	Clock Generator Sel., [RW]	Rsvd	SD Clock Ena., [RW]	Internal Clock Stable, [ROC]	Internal Clock Ena.,[RW]

SDCLK Frequency Select. This register is used to select the frequency of SDCLK pin. The definition of this field is dependent on the Host Controller Version.
(1) 8-bit Divided Clock Mode
This mode is supported by the Host Controller Version 1.00 and 2.00.

80h	base clock divided by 256
40h	base clock divided by 128
20h	base clock divided by 64
10h	base clock divided by 32
08h	base clock divided by 16
04h	base clock divided by 8
02h	base clock divided by 4
01h	base clock divided by 2
00h	Base clock (10MHz-63MHz)

(2) 10-bit Divided Clock Mode.
Host Controller Version 3.00 supports this mandatory mode instead of the 8-bit Divided Clock Mode. The length of divider is extended to10 bits and all divider values shall be supported.

3FFh	1/2046 Divided Clock
......	.......................
N	1/2N Divided Clock (Duty 50%)
......	.......................
002h	1/4 Divided Clock
001h	1/2 Divided Clock
000h	Base Clock (10MHz-255MHz)

(3) Programmable Clock Mode
Host Controller Version 3.00 supports this mode as optional. A non-zero value set to Clock Multiplier in the Capabilities register indicates support of this clock mode.

3FFh	Base Clock * M / 1024
......	.......................
N - 1	Base Clock * M / N
......	.......................
002h	Base Clock * M / 3
001h	Base Clock * M / 2
000h	Base Clock * M

Upper Bits of SDCLK Frequency Select. Host Controller Version 1.00 and 2.00 do not support these bits and they are treated as 00b fixed value (ROC).
Host Controller Version 3.00 shall support these bits to expand SDCLK Frequency Select to 10-bit. Bit 07-06 is assigned to bit 09-08 of clock divider in SDCLK Frequency Select.

Clock Generator Select. Host Controller Version 3.00 supports this bit. This bit is used to select the clock generator mode in SDCLK Frequency Select.
If the Programmable Clock Mode is supported (non-zero value is set to Clock Multiplier in the Capabilities register), this bit attribute is RW, and if not supported, this bit attribute is RO and zero is read.

This bit depends on the setting of Preset Value Enable in the Host Control 2 register.
If the Preset Value Enable = 0, this bit is set by Host Driver.
If the Preset Value Enable = 1, this bit is automatically set to a value specified in one of Preset Value registers.
'1' - Programmable Clock Mode;
'0' - Divided Clock Mode;

SD Clock Enable. The Host Controller shall stop SDCLK when writing this bit to 0. SDCLK Frequency Select can be changed when this bit is 0. Then, the Host Controller shall maintain the same clock frequency until SDCLK is stopped (Stop at SDCLK=0). If the Card Inserted in the Present State register is cleared, this bit shall be cleared.
'1' - Enable;
'0' - Disable;

Internal Clock Stable bit is set to 1 when SD Clock is stable after writing to Internal Clock Enable in this register to 1. The SD Host Driver shall wait to set SD Clock Enable until this bit is set to 1.
Note: This is useful when using PLL for a clock oscillator that requires setup time.
'1' - Ready;
'0' - Not ready;

Internal Clock Enable bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt. The Host Controller should stop its internal clock to go very low power state. Still, registers shall be able to be read and written. Clock starts to oscillate when this bit is set to 1. When clock oscillation is stable, the Host Controller shall set Internal Clock Stable in this register to 1. This bit shall not affect card detection.
'1' - Oscillate;
'0' - Stop;

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###Timeout Control Register (Offset 02Eh) At the initialization of the Host Controller, the Host Driver shall set the Data Timeout Counter Value according to the Capabilities register.

D07-----D04	D03-----D00
Rsvd	Data Timeout Counter Value, [RW]

Data Timeout Counter Value. This value determines the interval by which DAT line timeouts are detected. For more information about timeout generation, refer to the Data Timeout Error in the Error Interrupt Status register. Timeout clock frequency will be generated by dividing the base clock TMCLK value by this value. When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register).

1111b	Reserved
1110b	TMCLK x 2 27
..............	..................
0001b	TMCLK x 2 14
0000b	TMCLK x 2 13

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###Software Reset Register (Offset 02Fh) A reset pulse is generated when writing 1 to each bit of this register. After completing the reset, the Host Controller shall clear each bit. Because it takes some time to complete software reset, the Host Driver shall confirm that these bits are 0.

D07-----D03	D02	D01	D00
Rsvd	SW Rst For DAT Line, [RWAC]	SW Rst For CMD Line, [RWAC]	SW Rst For All, [RWAC]

Software Reset For DAT Line. Only part of data circuit is reset. DMA circuit is also reset.
The following registers and bits are cleared by this bit:

Buffer Data Port register
Buffer is cleared and initialized
Present State register
Buffer Read Enable
Buffer Write Enable
Read Transfer Active
Write Transfer Active
DAT Line Active
Command Inhibit (DAT)
Block Gap Control register
Continue Request
Stop At Block Gap Request
Normal Interrupt Status register
Buffer Read Ready
Buffer Write Ready*
DMA Interrupt
Block Gap Event
Transfer Complete
'1' - Reset;
'0' - Work;

Software Reset For CMD Line. Only part of command circuit is reset. The following registers and bits are cleared by this bit:
Present State register
Command Inhibit (CMD)
Normal Interrupt Status register
Command Complete
'1' - Reset;
'0' - Work;

Software Reset For All. This reset affects the entire Host Controller except for the card detection circuit. Register bits of type ROC, RW, RW1C, RWAC are cleared to 0. During its initialization, the Host Driver shall set this bit to 1 to reset the Host Controller. The Host Controller shall reset this bit to 0 when Capabilities registers are valid and the Host Driver can read them. Additional use of Software Reset For All may not affect the value of the Capabilities registers. If this bit is set to 1, the host driver should issue reset command and reinitialize the memory card.
'1' - Reset;
'0' - Work;

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###Normal Interrupt Status Register (Offset 030h) The Normal Interrupt Status Enable affects reads of this register, but Normal Interrupt Signal Enable does not affect these reads. An interrupt is generated when the Normal Interrupt Signal Enable is enabled and at least one of the status bits is set to 1. Writing 1 to a bit of RW1C attribute clears it; writing 0 keeps the bit unchanged. Writing 1 to a bit of ROC attribute keeps the bit unchanged. More than one status can be cleared with a single register write. The Card Interrupt is cleared when the card stops asserting the interrupt; that is, when the Card Driver services the interrupt condition.

D15	D14-D13	D12	D11	D10	D09	D08	D07	D06	D05	D04	D03	D02	D01	D00
Error Int., [ROC]	*Rsvd	Re-Tuning Event, [ROC]*	INT_C, [ROC]	INT_B, [ROC]	INT_A, [ROC]	Card Int., [ROC]	Card Removal, [RW1C]	Card Insertion, [RW1C]	Buff Read Ready, [RW1C]	Buff Write Ready, [RW1C]	DMA Int., [RW1C]	Block Gap Event, [RW1C]	Transfer Complete, [RW1C]	Command Complete, [RW1C]

Error Interrupt. If any of the bits in the Error Interrupt Status register are set, then this bit is set. Therefore the Host Driver can efficiently test for an error by checking this bit first. This bit is read only.
'1' - Error;
'0' - No Error;

Re-Tuning Event. This status is set if Re-Tuning Request in the Present State register changes from 0 to 1.
Host Controller requests Host Driver to perform re-tuning for next data transfer. Current data transfer (not large block count) can be completed without re-tuning.
'1' - Re-Tuning should be performed;
'0' - Re-Tuning is not required;

INT_C. This status is set if INT_C is enabled and INT_C# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_C interrupt factor. Refer to the Shared Bus Control register.
'1' - INT_C is detected;
'0' - No interrupt is detected;

INT_B. This status is set if INT_B is enabled and INT_B# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_B interrupt factor. Refer to the Shared Bus Control register.
'1' - INT_B is detected;
'0' - No interrupt is detected;

INT_A. This status is set if INT_A is enabled and INT_A# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_A interrupt factor. Refer to the Shared Bus Control register.
'1' - INT_B is detected;
'0' - No interrupt is detected;

Card Interrupt. Writing this bit to 1 does not clear this bit. It is cleared by resetting the memory card interrupt factor. In 1-bit mode, the Host Controller shall detect the Card Interrupt without SD Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, so there are some sample delays between the interrupt signal from the memory card and the interrupt to the Host System.
'1' - Generate Card Interrupt;
'0' - No Card Interrupt;

Card Removal. This status is set if the Card Inserted in the Present State register changes from 1 to 0.
When the Host Driver writes this bit to 1 to clear this status, the status of the Card Inserted in the Present State register should be confirmed. Because the card detect state may possibly be changed when the Host Driver clear this bit and interrupt event may not be generated.
'1' - Card removed;
'0' - Card state stable or Debouncing;

Card Insertion. This status is set if the Card Inserted in the Present State register changes from 0 to 1.
When the Host Driver writes this bit to 1 to clear this status, the status of the Card Inserted in the Present State register should be confirmed. Because the card detect state may possibly be changed when the Host Driver clear this bit and interrupt event may not be generated.
'1' - Card inserted;
'0' - Card state stable or Debouncing;

Buffer Read Ready. This status is set if the Buffer Read Enable changes from 0 to 1. Refer to the Buffer Read Enable in the Present State register.
While performing tuning procedure (Execute Tuning is set to 1), Buffer Read Ready is set to 1 for every CMD19 execution.
'1' - Ready to read buffer;
'0' - Not ready to read buffer;

Buffer Write Ready. This status is set if the Buffer Write Enable changes from 0 to 1. Refer to the Buffer Write Enable in the Present State register.
'1' - Ready to write buffer;
'0' - Not ready to write buffer;

DMA Interrupt. This status is set if the Host Controller detects the Host SDMA Buffer boundary during transfer. Refer to the Host SDMA Buffer Boundary in the Block Size register.
Other DMA interrupt factors may be added in the future. In case of ADMA, by setting Int field in the descriptor table, Host Controller generates this interrupt. Suppose that it is used for debugging. This interrupt shall not be generated after the Transfer Complete.
'1' - DMA Interrupt is generated;
'0' - No DMA Interrupt;

Block Gap Event. If the Stop At Block Gap Request in the Block Gap Control register is set, this bit is set when both a read / write transaction is stopped at a block gap. If Stop At Block Gap Request is not set to 1, this bit is not set to 1.
'1' - Transaction stopped at block gap;
'0' - No Block Gap Event;

Transfer Complete. This bit is set when a read / write transfer and a command with busy is completed. The table below shows that Transfer Complete has higher priority than Data Timeout Error. If both bits are set to 1, execution if a command can be considered to be completed.

Transfer Complete	Data Timeout Error	Meaning of the status
0	0	Interrupted by another factor
0	1	Timeout occur during transfer
1	Don't care	Command Execution complete

'1' - Command execution is completed
'0' - Not complete
While performing tuning procedure (Execute Tuning is set to 1), Transfer Complete is not set to 1.

Command Complete. This bit is set when get the end bit of the command response. Auto CMD12 and Auto CMD23 consist of two responses. Command Complete is not generated by the response of CMD12 or CMD23 but generated by the response of a read/write command.
Refer to Command Inhibit (CMD) in the Present State register for how to control this bit.

The table below shows that Command Timeout Error has higher priority than Command Complete. If both bits are set to 1, it can be considered that the response was not received correctly.

Command Complete	Command Timeout Error	Meaning of the status
0	0	Interrupted by another factor
Don't Care	1	Response not received within 64 SDCLK cycles.
1	0	Response received

'1' - Command execution is completed
'0' - Not complete

---

###Error Interrupt Status Register (Offset 032h) Signals defined in this register can be enabled by the Error Interrupt Status Enable register, but not by the Error Interrupt Signal Enable register. The interrupt is generated when the Error Interrupt Signal Enable is enabled and at least one of the statuses is set to 1. Writing to 1 clears the bit and writing to 0 keeps the bit unchanged. More than one status can be cleared at the one register write.

D15-----D12	D11	D10	D09	D08	D07	D06	D05	D04	D03	D02	D01	D00
Vendor Specific Error Status, RW1C	Rsvd	Tuning Error	ADMA Error	Auto CMD Error	Current Limit Error	Data End Bit Error	Data CRC Error	Data Timeout Error	Command Index Error	Command End Bit Error	Command CRC Error	Command Timeout Error

Vendor Specific Error Status. Additional status bits can be defined in this register by the vendor.

Tuning Error. This bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure (Occurrence of an error during tuning procedure is indicated by Sampling Select). By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. To reset tuning circuit, Sampling Clock shall be set to 0 before executing tuning procedure. The Tuning Error is higher priority than the other error interrupts generated during data transfer. By detecting Tuning Error, the Host Driver should discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from tuning circuit error.
'1' - Error;
'0' - No Error;

ADMA Error. This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register.
In addition, the Host Controller generates this Interrupt when it detects invalid descriptor data (Valid=0) at the ST_FDS state. ADMA Error State in the ADMA Error Status indicates that an error occurs in ST_FDS state. The Host Driver may find that Valid bit is not set at the error descriptor.
'1' - Error;
'0' - No Error;

Auto CMD Error. Auto CMD12 and Auto CMD23 use this error status. This bit is set when detecting that one of the bits D00-D04 in Auto CMD Error Status register has changed from 0 to 1. In case of Auto CMD12, this bit is set to 1, not only when the errors in Auto CMD12 occur but also when Auto CMD12 is not executed due to the previous command error.
'1' - Error;
'0' - No Error;

Current Limit Error. By setting the SD Bus Power bit in the Power Control register, the Host Controller is requested to supply power for the SD Bus. If the Host Controller supports the Current Limit function, it can be protected from an illegal card by stopping power supply to the card in which case this bit indicates a failure status. Reading 1 means the Host Controller is not supplying power to SD card due to some failure. Reading 0 means that the Host Controller is supplying power and no error has occurred. The Host Controller may require some sampling time to detect the current limit. If the Host Controller does not support this function, this bit shall always be set to 0.
'1' - Power fail;
'0' - No Error;

Data End Bit Error. Occurs either when detecting 0 at the end bit position of read data which uses the DAT line or at the end bit position of the CRC Status.
'1' - Error;
'0' - No Error

Data CRC Error. Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC status having a value of other than "010".
'1' - Error;
'0' - No Error;

Data Timeout Error. This bit is set when detecting one of following timeout conditions.

1. Busy timeout for R1b,R5b type
2. Busy timeout after Write CRC status
3. Write CRC Status timeout
4. Read Data timeout.

'1' - Time out;
'0' - No Error;

Command Index Error. This bit is set if a Command Index error occurs in the command response.
'1' - Error;
'0' - No Error;

Command End Bit Error. This bit is set when detecting that the end bit of a command response is 0.
'1' - End Bit Error Generated;
'0' - No Error;

Command CRC Error. Command CRC Error is generated in two cases. If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response.
The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued. If the Host Controller drives the CMD line to 1 level, but detects 0 level on the CMD line at the next SD clock edge, then the Host Controller shall abort the command (Stop driving CMD line) and set this bit to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line conflict.
'1' - CRC Error Generated;
'0' - No Error;

Command Timeout Error. This bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command. If the Host Controller detects a CMD line conflict, in which case Command CRC Error shall also be set as shown in Table 2-25, this bit shall be set without waiting for 64 SD clock cycles because the command will be aborted by the Host Controller.
'1' - Timeout;
'0' - No Error;

The relation between Command CRC Error and Command Timeout Error is shown in table:

Command CRC Error	Command Timeout Error	Kinds of error
0	0	No error
0	1	Response Timeout Error
1	0	Response CRC Error
1	1	CMD line conflict

---

###Normal Interrupt Status Enable Register (Offset 034h), [RW] Setting to 1 enables Interrupt Status.

D15	D14-D13	D12	D11	D10	D09	D08	D07	D06	D05	D04	D03	D02	D01	D00
Fixed to 0, [RO]	Rsvd	Re-Tuning Event Status Ena	INT_C Status Ena	INT_B Status Ena	INT_A Status Ena	Card Int. Status Ena	Card Removal Status Ena	Card Insertion Status Ena	Buff Read Ready Status Ena	Buff Write Ready Status Ena	DMA Int Status Ena	Block Gap Event Status Ena	Trans. Complete Status Ena	Command Complete Status Ena

Re-Tuning Event Status Enable
'1' - Enabled;
'0' - Masked;

INT_C Status Enable. If this bit is set to 0, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to INT_C pin are cleared to prevent inadvertent interrupts.
'1' - Enabled;
'0' - Masked;

INT_B Status Enable. If this bit is set to 0, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to INT_B pin are cleared to prevent inadvertent interrupts.
'1' - Enabled;
'0' - Masked;

INT_A Status Enable. If this bit is set to 0, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to INT_A pin are cleared to prevent inadvertent interrupts.
'1' - Enabled;
'0' - Masked;

Card Interrupt Status Enable. If this bit is set to 0, the Host Controller shall clear interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. The Host Driver may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts.
'1' - Enabled;
'0' - Masked;

Card Removal Status Enable
'1' - Enabled;
'0' - Masked;

Card Insertion Status Enable
'1' - Enabled;
'0' - Masked;

Buffer Read Ready Status Enable
'1' - Enabled;
'0' - Masked;

Buffer Write Ready Status Enable
'1' - Enabled;
'0' - Masked;

DMA Interrupt Status Enable
'1' - Enabled;
'0' - Masked;

Block Gap Event Status Enable
'1' - Enabled;
'0' - Masked;

Transfer Complete Status Enable
'1' - Enabled;
'0' - Masked;

Command Complete Status Enable
'1' - Enabled;
'0' - Masked;

---

###Error Interrupt Status Enable Register (Offset 036h), [RW] Setting to 1 enables Interrupt Status.

D15-----D12	D11	D10	D09	D08	D07	D06	D05	D04	D03	D02	D01	D00
Vendor Specific Error Status Ena	Rsvd	Tuning Error Status Ena	ADMA Error Status Ena	Auto CMD Error Status Ena	Current Limit Error Status Ena	Data End Bit Error Status Ena	Data CRC Error Status Ena	Data Timeout Error Status Ena	Command Index Error Status Ena	Command End Bit Error Status Ena	Command CRC Error Status Ena	Command Timeout Error Status Ena

Vendor Specific Error Status Ena
'1' - Enabled;
'0' - Masked;

Tuning Error Status Ena
'1' - Enabled;
'0' - Masked;

ADMA Error Status Ena
'1' - Enabled;
'0' - Masked;

Auto CMD Error Status Ena
'1' - Enabled;
'0' - Masked;

Current Limit Error Status Ena
'1' - Enabled;
'0' - Masked;

Data End Bit Error Status Ena
'1' - Enabled;
'0' - Masked;

Data CRC Error Status Ena
'1' - Enabled;
'0' - Masked;

Data Timeout Error Status Ena
'1' - Enabled;
'0' - Masked;

Command Index Error Status Ena
'1' - Enabled;
'0' - Masked;

Command End Bit Error Status Ena
'1' - Enabled;
'0' - Masked;

Command CRC Error Status Ena
'1' - Enabled;
'0' - Masked;

Command Timeout Error Status Ena
'1' - Enabled;
'0' - Masked;

---

###Normal Interrupt Signal Enable Register (Offset 038h), [RW] This register is used to select which interrupt status is indicated to the Host System as the interrupt. These status bits all share the same1 bit interrupt line. Setting any of these bits to 1 enables interrupt generation.

D15	D14-D13	D12	D11	D10	D09	D08	D07	D06	D05	D04	D03	D02	D01	D00
Fixed to 0, [RO]	Rsvd	Re-Tuning Event Signal Ena	INT_C Signal Ena	INT_B Signal Ena	INT_A Signal Ena	Card Int. Signal Ena	Card Removal Signal Ena	Card Insertion Signal Ena	Buff Read Ready Signal Ena	Buff Write Ready Signal Ena	DMA Int Signal Ena	Block Gap Event Signal Ena	Trans. Complete Signal Ena	Command Complete Signal Ena

Re-Tuning Event Signal Enable
'1' - Enabled;
'0' - Masked;

INT_C Signal Enable
'1' - Enabled;
'0' - Masked;

INT_B Signal Enable
'1' - Enabled;
'0' - Masked;

INT_A Signal Enable
'1' - Enabled;
'0' - Masked;

Card Interrupt Signal Enable
'1' - Enabled;
'0' - Masked;

Card Removal Signal Enable
'1' - Enabled;
'0' - Masked;

Card Insertion Signal Enable
'1' - Enabled;
'0' - Masked;

Buffer Read Ready Signal Enable
'1' - Enabled;
'0' - Masked;

Buffer Write Ready Signal Enable
'1' - Enabled;
'0' - Masked;

DMA Interrupt Signal Enable
'1' - Enabled;
'0' - Masked;

Block Gap Event Signal Enable
'1' - Enabled;
'0' - Masked;

Transfer Complete Signal Enable
'1' - Enabled;
'0' - Masked;

Command Complete Signal Enable
'1' - Enabled;
'0' - Masked;

---

###Error Interrupt Signal Enable Register (Offset 03Ah), [RW] This register is used to select which interrupt status is notified to the Host System as the interrupt. These status bits all share the same 1 bit interrupt line. Setting any of these bits to 1 enables interrupt generation.

D15-----D12	D11	D10	D09	D08	D07	D06	D05	D04	D03	D02	D01	D00
Vendor Specific Error Signal Ena	Rsvd	Tuning Error Signal Ena	ADMA Error Signal Ena	Auto CMD Error Signal Ena	Current Limit Error Signal Ena	Data End Bit Error Signal Ena	Data CRC Error Signal Ena	Data Timeout Error Signal Ena	Command Index Error Signal Ena	Command End Bit Error Signal Ena	Command CRC Error Signal Ena	Command Timeout Error Signal Ena

Vendor Specific Error Signal Enable
'1' - Enabled;
'0' - Masked;

Tuning Error Signal Enable
'1' - Enabled;
'0' - Masked;

ADMA Error Signal Enable
'1' - Enabled;
'0' - Masked;

Auto CMD Error Signal Enable
'1' - Enabled;
'0' - Masked;

Current Limit Error Signal Enable
'1' - Enabled;
'0' - Masked;

Data End Bit Error Signal Enable
'1' - Enabled;
'0' - Masked;

Data CRC Error Signal Enable
'1' - Enabled;
'0' - Masked;

Data Timeout Error Signal Enable
'1' - Enabled;
'0' - Masked;

Command Index Error Signal Enable
'1' - Enabled;
'0' - Masked;

Command End Bit Error Signal Enable
'1' - Enabled;
'0' - Masked;

Command CRC Error Signal Enable
'1' - Enabled;
'0' - Masked;

Command Timeout Error Signal Enable
'1' - Enabled;
'0' - Masked;

---

###Auto CMD Error Status Register (Offset 03Ch), [ROC] This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD23. The Host driver can determine what kind of Auto CMD12 / CMD23 errors occur by this register. Auto CMD23 errors are indicated in bit 04-01.This register is valid only when the Auto CMD Error is set.

D15-----D08	D07	D06-D05	D04	D03	D02	D01	D00
Rsvd	Command Not Issued By Auto CMD12 Error	Rsvd	Auto CMD Index Error	Auto CMD End Bit Error	Auto CMD CRC Error	Auto CMD Timeout Error	Auto CMD12 Not Executed

Command Not Issued By Auto CMD12 Error. Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register.
This bit is set to 0 when Auto CMD Error is generated by Auto CMD23.
'1' - Not issued;
'0' - No error;

Auto CMD Index Error. This bit is set if the Command Index error occurs in response to a command.
'1' - Error;
'0' - No error;

Auto CMD End Bit Error. This bit is set when detecting that the end bit of command response is 0.
'1' - End Bit Error Generated;
'0' - No error;

Auto CMD CRC Error. This bit is set when detecting a CRC error in the command response.
'1' - CRC Error Generated;
'0' - No error;

Auto CMD Timeout Error. This bit is set if no response is returned within 64 SDCLK cycles from the end bit of command.
If this bit is set to1, the other error status bits (D04-D02) are meaningless.
'1' - Time out;
'0' - No error;

Auto CMD12 Not Executed. If memory multiple block data transfer is not started due to command error, this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the Host Controller cannot issue Auto CMD12 to stop memory multiple block data transfer due to some error. If this bit is set to 1, other error status bits (D04-D01) are meaningless.
This bit is set to 0 when Auto CMD Error is generated by Auto CMD23.
'1' - Not executed;
'0' - No error;

The relation between Auto CMD CRC Error and Auto CMD Timeout Error is shown in Table.

Auto CMD CRC Error	Auto Time out Error	Kinds of error
0	0	No error
0	1	Response Timeout Error
1	0	Response CRC Error
1	1	CMD line conflict

---

###Capabilities Register (Offset 040h), [HwInit] This register provides the Host Driver with information specific to the Host Controller implementation. The Host Controller may implement these values as fixed or loaded from flash memory during power on initialization. Refer to Software Reset For All in the Software Reset register for loading from flash memory and completion timing control.

D63-----D56	D55-----D48	D47-D46	D45	D44	D43-----D40	D39	D38	D37	D36	D35	D34	D33	D32
Rsvd	Clock Multiplier	Re-Tuning Modes	Use Tuning for SDR50	Rsvd	Timer Count for Re-Tuning	Rsvd	Driver Type D Support	Driver Type C Support	Driver Type A Support	Rsvd	DDR50 Support	SDR104 Support	SDR50 Support

D31-D30	D29	D28	D27	D26	D25	D24	D23	D22	D21	D20	D19	D18	D17-D16	D15-----D08	D07	D06	D05-----D00
Slot Type	Asynchronous Int Support	64-bit System Bus Support	Rsvd	Voltage Support 1.8V	Voltage Support 3.0V	Voltage Support 3.3V	Suspend/Resume Support	SDMA Support	High Speed Support	Rsvd	ADMA2 Support	8-bit Support for Embedded Device	Max Block Length	Base Clock Frequency For SD Clock	Timeout Clock Unit	Rsvd	Timeout Clock Frequency

Clock Multiplier. This field indicates clock multiplier value of programmable clock generator.Refer to Clock Control register. Setting 00h means that Host Controller does not support programmable clock generator.

00h	Clock Multiplier is Not Supported
01h	Clock Multiplier M = 2
02h	Clock Multiplier M = 3
...	............
FFh	Clock Multiplier M = 256

Re-Tuning Modes. This field selects re-tuning method and limits the maximum data length.

Bits47-46	Re-Tuning Mode	Re-Tuning Method	Data Length
00b	Mode 1	Timer	4MB (Max.)
01b	Mode 2	Timer and Re-Tuning Request	4MB (Max.)
10b	Mode 3	Auto Re-Tuning (for transfer) Timer and Re-Tuning Request	Any
11b	Reserved	Reserved	Reserved

There are two re-tuning timings: Re-Tuning Request controlled by the Host Controller and expiration of a Re-Tuning Timer controlled by the Host Driver. By receiving either timing, the Host Driver executes the re-tuning procedure just before a next command issue. The maximum data length per read/write command is restricted so that re-tuning procedures can be inserted during data transfers. In order to get more detailed info about Re-Tuning modes see SD Host Controller Simplified Specification Version 3.00, Chapter 2.2.25

Use Tuning for SDR50. If this bit is set to 1, this Host Controller requires tuning to operate SDR50. (Tuning is always required to operate SDR104.) '1' - SDR50 requires tuning;
'0' - SDR50 does not require tuning;

Timer Count for Re-Tuning. This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 0 disables Re-Tuning Timer.

0h	Re-Tuning Timer disabled
1h	1 seconds
2h	2 seconds
3h	4 seconds
4h	8 seconds
...	..........
n	2^(n-1) seconds
...	..........
Bh	1024 seconds
Eh-Ch	Reserved
Fh	Get information from other source

Driver Type D Support. This bit indicates support of Driver Type D for 1.8 Signaling.
'1' - Driver Type D is Supported;
'0' - Driver Type D is Not Supported;

Driver Type C Support. This bit indicates support of Driver Type C for 1.8 Signaling.
'1' - Driver Type C is Supported;
'0' - Driver Type C is Not Supported;

Driver Type A Support. This bit indicates support of Driver Type A for 1.8 Signaling.
'1' - Driver Type C is Supported;
'0' - Driver Type C is Not Supported;

DDR50 Support.
'1' - DDR50 is Supported;
'0' - DDR50 is Not Supported;

SDR104 Support.
SDR104 requires tuning.
'1' - SDR104 is Supported;
'0' - SDR104 is Not Supported;

SDR50 Support.
If SDR104 is supported, this bit shall be set to 1. Bit 45 indicates whether SDR50 requires tuning or not.
'1' - SDR50 is Supported;
'0' - SDR50 is Not Supported;

Slot Type. This field indicates usage of a slot by a specific Host System. (A host controller register set is defined per slot.) Embedded Slot for One Device (01b) means that only one non-removable device is connected to a SD bus slot. Shared Bus Slot (10b) can be set if Host Controller supports Shared Bus Control register.

The Standard Host Driver controls only a removable card or one embedded device connected to a SD bus slot. If a slot is configured for shared bus (10b), the Standard Host Driver does not control embedded devices connected to a shared bus. Shared bus slot is controlled by a specific host driver developed by a Host System.

00b	Removable Card Slot
01b	Embedded Slot for One Device
10b	Shared Bus Slot
11b	Reserved

Asynchronous Interrupt Support. Refer to SDIO Specification Version 3.00 about asynchronous interrupt.
'1' - Asynchronous Interrupt Supported;
'0' - Asynchronous Interrupt Not Supported;

64-bit System Bus Support. Setting 1 to this bit indicates that the Host Controller supports 64-bit address descriptor mode and is connected to 64-bit address system bus.

Voltage Support 1.8V. Embedded system can use 1.8V power supply.
'1' - 1.8V Supported;
'0' - 1.8V Not Supported;

Voltage Support 3.0V.
'1' - 3.0V Supported;
'0' - 3.0V Not Supported;

Voltage Support 3.3V.
'1' - 3.3V Supported;
'0' - 3.3V Not Supported;

Suspend/Resume Support.
This bit indicates whether the Host Controller supports Suspend / Resume functionality. If this bit is 0, the Host Driver shall not issue either Suspend or Resume commands because the Suspend and Resume mechanism (Refer to Section 1.6 of SD Host Controller Simplified Specification Version 3.00) is not supported.
'1' - Supported;
'0' - Not Supported;

SDMA Support.
This bit indicates whether the Host Controller is capable of using SDMA to transfer data between system memory and the Host Controller directly.
'1' - SDMA Supported;
'0' - SDMA Not Supported;

High Speed Support.
This bit indicates whether the Host Controller and the Host System support High Speed mode and they can supply SD Clock frequency from 25MHz to 50MHz. '1' - High Speed Supported;
'0' - High Speed Not Supported;

ADMA2 Support.
This bit indicates whether the Host Controller is capable of using ADMA2.
'1' - ADMA2 Supported;
'0' - ADMA2 Not Supported;

8-bit Support for Embedded Device.
This bit indicates whether the Host Controller is capable of using 8-bit bus width mode. This bit is not effective when Slot Type is set to 10b. In this case, refer to Bus Width Preset in the Shared Bus resister.
'1' - 8-bit Bus Width Supported;
'0' - 8-bit Bus Width Not Supported;

Max Block Length.
This value indicates the maximum block size that the Host Driver can read and write to the buffer in the Host Controller. The buffer shall transfer this block size without wait cycles. Three sizes can be defined as indicated below. It is noted that transfer block length shall be always 512 bytes for SD Memory Cards regardless this field.

00	512(byte)
01	1024
10	2048
11	Reserved

Base Clock Frequency For SD Clock. This value indicates the base (maximum) clock frequency for the SD Clock. Definition of this field depends on Host Controller Version.
(1) 6-bit Base Clock Frequency
This mode is supported by the Host Controller Version 1.00 and 2.00. Upper 2 bits are not effective and always 0. Unit values are 1MHz. The supported clock range is 10MHz to 63MHz.

11xx xxxxb	Not supported
0011 1111b	63MHz
.........	..........
0000 0010b	2MHz
0000 0001b	1MHz
0000 0000b	Get information via another method

(2) 8-bit Base Clock Frequency
This mode is supported by the Host Controller Version 3.00. Unit values are 1MHz. The supported clock range is 10MHz to 255MHz.

FFh|255MHz ....|.......... 02h|2MHz 01h|1MHz 00h|Get information via another method

If the real frequency is 16.5MHz, the lager value shall be set 0001 0001b (17MHz) because the Host Driver use this value to calculate the clock divider value (Refer to the SDCLK Frequency Select in the Clock Control register.) and it shall not exceed upper limit of the SD Clock frequency. If these bits are all 0, the Host System has to get information via another method.

Timeout Clock Unit. This bit shows the unit of base clock frequency used to detect Data Timeout Error.
'0' - KHz;
'1' - MHz;

Timeout Clock Frequency. This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock Unit defines the unit of this field's value.
Timeout Clock Unit =0 [KHz] unit: 1KHz to 63KHz
Timeout Clock Unit =1 [MHz] unit: 1MHz to 63MHz

Not 0	1KHz to 63KHz or 1MHz to 63MHz
00 0000b	Get information via another method

---

###ADMA System Address Register (Offset 058h), [RW] This register contains the physical Descriptor address used for ADMA data transfer.

This register holds byte address of executing command of the Descriptor table. 32-bit Address Descriptor uses lower 32-bit of this register. At the start of ADMA, the Host Driver shall set start address of the Descriptor table. The ADMA increments this register address, which points to next line, when every fetching a Descriptor line. When the ADMA Error Interrupt is generated, this register shall hold valid Descriptor address depending on the ADMA state. The Host Driver shall program Descriptor Table on 32-bit boundary and set 32-bit boundary address to this register. ADMA2 ignores lower 2-bit of this register and assumes it to be 00b.

32-bit Address ADMA

Register Value	32-bit System Address
xxxxxxxx 00000000h	00000000h
xxxxxxxx 00000004h	00000004h
xxxxxxxx 00000008h	00000008h
xxxxxxxx 0000000Ch	0000000Ch
......	......
xxxxxxxx FFFFFFFCh	FFFFFFFCh

64-bit Address ADMA

Register Value	64-bit System Address
00000000 00000000h	00000000 00000000h
00000000 00000004h	00000000 00000004h
00000000 00000008h	00000000 00000008h
00000000 0000000Ch	00000000 0000000Ch
......	......
FFFFFFFF FFFFFFFCh	FFFFFFFF FFFFFFFCh

---

###Host Controller Version Register (Offset 0FEh), [HwInit]

D15 ----- D08	D07 ----- D00
Vendor Version Number	Specification Version Number

Vendor Version Number. This status is reserved for the vendor version number. The Host Driver should not use this status.

Specification Version Number. This status indicates the Host Controller Spec. Version. The upper and lower 4-bits indicate the version.

00h	SD Host Specification Version 1.00
01h	SD Host Specification Version 2.00. Including the feature of the ADMA and Test Register
02h	SD Host Specification Version 3.00
others	Reserved

---