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HW RAID 0
Baktiiar Kukanov edited this page Dec 11, 2016
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###Summary In order to increase the RAID 0 speed, we decided to use hardware raid system. We need to design IP core which will stripe the data across the eMMC host controllers. We are planing to combine 2 eMMC Host Controllers into single one, where DMA's, command line's and data line's will be separate. Due to this we need to manage this 2 HC like single one with control block. One of the HC will be like master and most of the operation will be done by it.
###Requirements of HW RAID 0
- Needed to initialize the eMMC card through the HW RAID 0 like one single device with big memory
- Needed to organize the driver extended CSD reading from eMMC cards through data line, due to memory size increase needed to implement some logics where CSD will be recalculated
- Command line response analyse (error giving card identification mostly)
- Control block (reading block descriptor, addresses for DMA's)
- Needed to implement some logics where will be updated super blocks
- State Machine
eMMC Host Controller ver 3.0
- Pars board design
- Element layouts
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AXI Host Controller for eMMC
* Control register map
- Summarise control register set
- Configuration register type
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Detailed register description
- Argument2 reg
- Block Size reg
- Block Count reg
- Argument1 reg
- Transfer mode reg
- Command reg
- Response0 reg
- Response1 reg
- Response2 reg
- Response3 reg
- Present State reg
- Host control1 reg
- Clock control reg
- Timeout control reg
- Software reset reg
- Normal Interrupt status reg
- Error Interrupt status reg
- Normal Interrupt status enable reg
- Error Interrupt status enable reg
- Normal Interrupt signal enable reg
- Error Interrupt signal enable reg
- Auto CMD Error Status reg
- Capabilities reg
- ADMA System Address reg
- Host Control version reg * Advanced DMA
- Description
- ADMA work principles
- ADMA Implementation * AutoCMD23 feature
- Description
- The-feature-work-principles
- Feature implementation * Reference list * Performance tests