Add Loadable smart amp support

lmdk/include/adsp_stddef.h

@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// Copyright(c) 2021 Intel Corporation. All rights reserved.
+
+
+#ifndef _ADSP_STDDEF_H_
+#define _ADSP_STDDEF_H_
+
+
+#include <stddef.h>
+#include <stdint.h>
+
+#if  defined(XTENSA_TOOLSCHAIN) || defined(__XCC__)
+  #include <xtensa/config/tie.h>
+#endif
+
+#ifndef XCHAL_CP1_SA_ALIGN
+  #define XCHAL_CP1_SA_ALIGN sizeof(intptr_t)
+#endif
+
+
+#ifdef __GNUC__
+  #define ALIGNED(x) __attribute__((aligned((x))))
+#else
+  #define ALIGNED(x)
+#endif
+
+#define DCACHE_ALIGNED ALIGNED(64)
+
+#ifdef __XTENSA__
+  #define RESTRICT __restrict
+#else
+  #define RESTRICT
+#endif
+
+#define MODULE_INSTANCE_ALIGNMENT 4096
+
+#ifndef MIN
+#define MIN(a,b) ((a<b) ? a : b)
+#endif
+#ifndef MAX
+#define MAX(a,b) ((a<b) ? b : a)
+#endif
+
+#ifdef __cplusplus
+namespace intel_adsp
+{
+struct ModulePlaceholder {};
+}
+inline void* operator new(size_t size, intel_adsp::ModulePlaceholder* placeholder) throw()
+{
+    (void)size;
+    return placeholder;
+}
+#endif //#ifdef __cplusplus
+
+
+#define ADSP_BUILD_INFO_FORMAT 0
+
+/*! \cond INTERNAL */
+typedef union AdspApiVersion
+{
+    uint32_t full;
+    struct
+    {
+        uint32_t minor    : 10;
+        uint32_t middle   : 10;
+        uint32_t major    : 10;
+        uint32_t reserved : 2;
+    } fields;
+} AdspApiVersion;
+/*! \endcond INTERNAL */
+
+/*! \cond INTERNAL */
+typedef const struct
+{
+    uint32_t FORMAT;
+    AdspApiVersion API_VERSION_NUMBER;
+} AdspBuildInfo;
+/*! \endcond INTERNAL */
+
+/*! Log level priority enumeration. */
+typedef enum log_priority {
+	/*! Critical message. */
+	L_CRITICAL,
+	/*! Error message. */
+	L_ERROR,
+	/*! High importance log level. */
+	L_HIGH,
+	/*! Warning message. */
+	L_WARNING,
+	/*! Medium importance log level. */
+	L_MEDIUM,
+	/*! Low importance log level. */
+	L_LOW,
+	/*! Information. */
+	L_INFO,
+	/*! Verbose message. */
+	L_VERBOSE,
+	L_DEBUG,
+	L_MAX,
+} AdspLogPriority,
+	log_priority_e;
+struct AdspLogHandle;
+typedef struct AdspLogHandle AdspLogHandle;
+
+
+#endif //_ADSP_STDDEF_H_

lmdk/include/arch/lib/cache.h

@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2017 Intel Corporation. All rights reserved.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ */
+
+#ifdef __SOF_LIB_CACHE_H__
+
+#ifndef __ARCH_LIB_CACHE_H__
+#define __ARCH_LIB_CACHE_H__
+
+//#include <xtensa/config/core-isa.h>
+
+#define DCACHE_LINE_SIZE	XCHAL_DCACHE_LINESIZE
+
+#if !defined(__ASSEMBLER__) && !defined(LINKER)
+
+#include <../include/arch/xtensa/hal.h>
+//#include <sof/compiler_attributes.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#ifdef CONFIG_COMPILER_WORKAROUND_CACHE_ATTR
+#include <sof/drivers/cache_attr.h>
+#endif
+
+#define SRAM_UNCACHED_ALIAS	0x20000000
+
+#ifdef CONFIG_IMX
+
+#ifdef CONFIG_COMPILER_WORKAROUND_CACHE_ATTR
+/*
+ * We want to avoid buggy compiler optimization (function inlining).
+ * So we replace the call to glb_addr_attr() from glb_is_cached()
+ * with a function pointer that is initialized in
+ * src/arch/xtensa/driver/cache_attr.c
+ */
+#define is_cached(address) glb_is_cached(address)
+
+#else /* CONFIG_COMPILER_WORKAROUND_CACHE_ATTR */
+/*
+ * The _memmap_cacheattr_reset linker script variable has
+ * dedicate cache attribute for every 512M in 4GB space
+ * 1: write through
+ * 2: cache bypass
+ * 4: write back
+ * F: invalid access
+ */
+extern uint32_t _memmap_cacheattr_reset;
+
+/*
+ * Since each hex digit keeps the attributes for a 512MB region,
+ * we have the following address ranges:
+ * Address range       - hex digit
+ * 0        - 1FFFFFFF - 0
+ * 20000000 - 3FFFFFFF - 1
+ * 40000000 - 5FFFFFFF - 2
+ * 60000000 - 7FFFFFFF - 3
+ * 80000000 - 9FFFFFFF - 4
+ * A0000000 - BFFFFFFF - 5
+ * C0000000 - DFFFFFFF - 6
+ * E0000000 - FFFFFFFF - 7
+ */
+
+/*
+ * Based on the above information, get the address region id (0-7)
+ */
+#define _addr_range(address) (((uintptr_t)(address) >> 29) & 0x7)
+/*
+ * Get the position of the cache attribute for a certain memory region.
+ * There are 4 bits per hex digit.
+ */
+#define _addr_shift(address) ((_addr_range(address)) << 2)
+/*
+ * For the given address, get the corresponding hex digit
+ * from the linker script variable that contains the cache attributes
+ */
+#define _addr_attr(address) ((((uint32_t)(&_memmap_cacheattr_reset)) >> \
+			     (_addr_shift(address))) & 0xF)
+/*
+ * Check if the address is cacheable or not, by verifying the _addr_attr,
+ * which for cacheable addresses might be 1 or 4
+ */
+#define is_cached(address) ((_addr_attr(address) == 1) || \
+			    (_addr_attr(address) == 4))
+#endif /* CONFIG_COMPILER_WORKAROUND_CACHE_ATTR */
+
+#else /* CONFIG_IMX */
+#define is_cached(address) (!!((uintptr_t)(address) & SRAM_UNCACHED_ALIAS))
+#endif
+
+static inline void dcache_writeback_region(void __sparse_cache *addr, size_t size)
+{
+#if XCHAL_DCACHE_SIZE > 0
+	if (is_cached(addr))
+		xthal_dcache_region_writeback((__sparse_force void *)addr, size);
+#endif
+}
+
+static inline void dcache_writeback_all(void)
+{
+#if XCHAL_DCACHE_SIZE > 0
+	xthal_dcache_all_writeback();
+#endif
+}
+
+static inline void dcache_invalidate_region(void __sparse_cache *addr, size_t size)
+{
+#if XCHAL_DCACHE_SIZE > 0
+	if (is_cached(addr))
+		xthal_dcache_region_invalidate((__sparse_force void *)addr, size);
+#endif
+}
+
+static inline void dcache_invalidate_all(void)
+{
+#if XCHAL_DCACHE_SIZE > 0
+	xthal_dcache_all_invalidate();
+#endif
+}
+
+static inline void icache_invalidate_region(void *addr, size_t size)
+{
+#if XCHAL_ICACHE_SIZE > 0
+	xthal_icache_region_invalidate(addr, size);
+#endif
+}
+
+static inline void icache_invalidate_all(void)
+{
+#if XCHAL_ICACHE_SIZE > 0
+	xthal_icache_all_invalidate();
+#endif
+}
+
+static inline void dcache_writeback_invalidate_region(void __sparse_cache *addr, size_t size)
+{
+#if XCHAL_DCACHE_SIZE > 0
+	if (is_cached(addr))
+		xthal_dcache_region_writeback_inv((__sparse_force void *)addr, size);
+#endif
+}
+
+static inline void dcache_writeback_invalidate_all(void)
+{
+#if XCHAL_DCACHE_SIZE > 0
+	xthal_dcache_all_writeback_inv();
+#endif
+}
+
+#endif /* !defined(__ASSEMBLER__) && !defined(LINKER) */
+
+#endif /* __ARCH_LIB_CACHE_H__ */
+
+#else
+
+#error "This file shouldn't be included from outside of sof/lib/cache.h"
+
+#endif /* __SOF_LIB_CACHE_H__ */

lmdk/include/arch/lib/memory.h

@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2022 Intel Corporation. All rights reserved.
+ *
+ * Author: Marcin Rajwa <marcin.rajwa@linux.intel.com>
+ */
+
+#ifdef __SOF_LIB_MEMORY_H__
+
+#ifndef __PLATFORM_LIB_MEMORY_H__
+#define __PLATFORM_LIB_MEMORY_H__
+
+/* prioritize definitions in Zephyr SoC layer */
+//#ifdef __ZEPHYR__
+//#include <adsp_memory.h>
+//#endif
+//
+#include <../include/platform/memory.h>
+//#include <mem_window.h>
+//#include <sof/lib/cpu.h>
+#include <stdint.h>
+
+/* HP SRAM windows */
+#define WIN_BASE(n)			DT_REG_ADDR(DT_PHANDLE(MEM_WINDOW_NODE(n), memory))
+
+/* window 0 */
+#define SRAM_SW_REG_BASE		((uint32_t)(WIN_BASE(0) + WIN0_OFFSET))
+#define SRAM_SW_REG_SIZE		0x1000
+
+#define SRAM_OUTBOX_BASE		(SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
+#define SRAM_OUTBOX_SIZE		0x1000
+
+/* window 1 */
+#define SRAM_INBOX_BASE			((uint32_t)(WIN_BASE(1) + WIN1_OFFSET))
+#define SRAM_INBOX_SIZE			((uint32_t)WIN_SIZE(1))
+
+/* window 2 */
+#define SRAM_DEBUG_BASE			((uint32_t)(WIN_BASE(2) + WIN2_OFFSET))
+#define SRAM_DEBUG_SIZE			0x800
+
+#define SRAM_EXCEPT_BASE		(SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
+#define SRAM_EXCEPT_SIZE		0x800
+
+#define SRAM_STREAM_BASE		(SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
+#define SRAM_STREAM_SIZE		0x1000
+
+/* Stack configuration */
+#define SOF_STACK_SIZE			0x1000
+
+#define PLATFORM_HEAP_SYSTEM		CONFIG_CORE_COUNT /* one per core */
+#define PLATFORM_HEAP_SYSTEM_RUNTIME	CONFIG_CORE_COUNT /* one per core */
+#define PLATFORM_HEAP_RUNTIME		1
+#define PLATFORM_HEAP_RUNTIME_SHARED	1
+#define PLATFORM_HEAP_SYSTEM_SHARED	1
+#define PLATFORM_HEAP_BUFFER		2
+
+/**
+ * size of HPSRAM system heap
+ */
+#define HEAPMEM_SIZE 0xD0000
+
+#endif /* __PLATFORM_LIB_MEMORY_H__ */
+
+#else
+
+#error "This file shouldn't be included from outside of sof/lib/memory.h"
+
+#endif /* __SOF_LIB_MEMORY_H__ */