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Lower logical intrin and end-to-end demo #448

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merged 10 commits into from
Sep 1, 2021

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vinx13
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@vinx13 vinx13 commented Aug 18, 2021

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@vinx13 vinx13 force-pushed the feat/logical_intrin_tir branch 3 times, most recently from ec97cef to b6a2f06 Compare August 25, 2021 20:13
@vinx13 vinx13 changed the title [WIP] Lower logical intrin and end-to-end demo Lower logical intrin and end-to-end demo Aug 31, 2021
@vinx13 vinx13 force-pushed the feat/logical_intrin_tir branch 2 times, most recently from 228f3f7 to d7d5699 Compare August 31, 2021 23:33
@vinx13 vinx13 force-pushed the feat/logical_intrin_tir branch from d7d5699 to 8fd206c Compare August 31, 2021 23:34
@vinx13 vinx13 merged commit ca726d7 into tlc-pack:main Sep 1, 2021
yzh119 added a commit that referenced this pull request Sep 4, 2021
* upd

* normalize

* fix

* upd

* upd

* upd

* Readd instruction SampleShapeGenericTiles (#459)

* [Backport] MatchBuffer, BufferLocator & GetBlockReadWriteRegion (#460)

* [TensorIR] Support for match_buffer from subregion (#8585)

Co-authored-by: Junru Shao <junrushao1994@gmail.com>
Co-authored-by: Bohan Hou <32121147+spectrometerHBH@users.noreply.github.com>
Co-authored-by: Ruihang Lai <lairuihangdongdong@qq.com>
Co-authored-by: Hongyi Jin <3231950289@qq.com>
Co-authored-by: Wuwei Lin <wuwei@apache.org>
# Conflicts:
#	python/tvm/script/special_stmt.py
#	python/tvm/tir/transform/transform.py
#	src/tir/analysis/block_access_region_detector.cc
#	src/tir/analysis/buffer_access_lca_detector.cc
#	src/tir/transforms/lower_match_buffer.cc
#	tests/python/integration/test_lower.py
#	tests/python/unittest/test_tir_analysis_detect_buffer_access_lca.py
#	tests/python/unittest/test_tir_analysis_get_block_access_region.py
#	tests/python/unittest/test_tir_lower_match_buffer.py
#	tests/python/unittest/test_tir_transform_compact_buffer_region.py
#	tests/python/unittest/test_tvmscript_error_report.py

* [TIR] Fix opaque access in buffer locator pass and match_buffer in region detector (#8855)

* init

* fix

* Update src/tir/transforms/plan_update_buffer_allocation_location.cc

Co-authored-by: Ruihang Lai <lairuihangdongdong@qq.com>

* Update src/tir/transforms/plan_update_buffer_allocation_location.cc

Co-authored-by: Ruihang Lai <lairuihangdongdong@qq.com>

* address

Co-authored-by: Junru Shao <junrushao1994@gmail.com>
Co-authored-by: Ruihang Lai <lairuihangdongdong@qq.com>

* [TIR] GetBlockReadWriteRegion (#8875)

* [TIR] GetBlockReadWriteRegion

* Fix black issue

* Use constant reference for the interface

* Fix lint issue

* Catch the correct error class in logical layout test

Co-authored-by: Siyuan Feng <hzfengsy@vip.qq.com>
Co-authored-by: Junru Shao <junrushao1994@gmail.com>

* [BugFix] Fix Conv2d TensorCore Demo (#461)

* [Backport] LowerWarpMemory: remove unneeded shuffle when accessing from the same thread (#464)

* Lower logical intrin and end-to-end demo (#448)

* [WIP] Logical Layout lowering

* add intrin

* Logical inntrin lowering

* e2e demo

* LowerLogicalIntrin

* Remove num groups

* remove old demo

* rebase

* fix

* lower intrin pass

* Support nested software pipelining (#463)

* Support nested software pipelining

* Update test_schedule_software_pipeline.py

* upd

* upd

Co-authored-by: Bojian Zheng <bojian.zheng@mail.utoronto.ca>
Co-authored-by: Ruihang Lai <lairuihangdongdong@qq.com>
Co-authored-by: Siyuan Feng <hzfengsy@vip.qq.com>
Co-authored-by: Junru Shao <junrushao1994@gmail.com>
Co-authored-by: Wuwei Lin <wuwei@apache.org>
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@vinx13 Hi Wuwei! I noticed that after this PR getting merged, the cross-thread reduction unit tests all failed on branch main. Looks like the issue is due to these lines
https://github.com/Hzfengsy/tvm-tensorir/blob/ca726d77f25ee8b4fbbc799264f1514aa82ee57a/src/tir/transforms/lower_logical_intrin.cc#L95-L97
Since lowering cross-thread reduction introduces EvaluateNode and CallNode, these lines will be visited. And because we never register FLowerLogicalIntrin in the cross-thread reduction unit tests, the error is triggered.

Could you please take a look and fix the issue?

P.S. The error messages

Traceback (most recent call last):
  File "tensorir.py", line 55, in <module>
    print(tvm.lower(s.mod["main"], None, simple_mode=True))
  File "/home/rhlai/lrh-tensorir/python/tvm/driver/build_module.py", line 129, in lower
    return ffi.lower_primfunc(inp, name, simple_mode)
  File "/home/rhlai/lrh-tensorir/python/tvm/_ffi/_ctypes/packed_func.py", line 237, in __call__
    raise get_last_ffi_error()
tvm._ffi.base.TVMError: Traceback (most recent call last):
  [bt] (8) /home/rhlai/lrh-tensorir/build/libtvm.so(tvm::tir::StmtFunctor<tvm::tir::Stmt (tvm::tir::Stmt const&)>::InitVTable()::{lambda(tvm::runtime::ObjectRef const&, tvm::tir::StmtFunctor<tvm::tir::Stmt (tvm::tir::Stmt const&)>*)#13}::_FUN(tvm::runtime::ObjectRef const&, tvm::tir::StmtFunctor<tvm::tir::Stmt (tvm::tir::Stmt const&)>*)+0x40) [0x7fb554c01502]
  [bt] (7) /home/rhlai/lrh-tensorir/build/libtvm.so(tvm::tir::StmtFunctor<tvm::tir::Stmt (tvm::tir::Stmt const&)>::InitVTable()::{lambda(tvm::runtime::ObjectRef const&, tvm::tir::StmtFunctor<tvm::tir::Stmt (tvm::tir::Stmt const&)>*)#13}::operator()(tvm::runtime::ObjectRef const&, tvm::tir::StmtFunctor<tvm::tir::Stmt (tvm::tir::Stmt const&)>*) const+0x5b) [0x7fb554c014a3]
  [bt] (6) /home/rhlai/lrh-tensorir/build/libtvm.so(tvm::tir::LogicalIntrinMutator::VisitStmt_(tvm::tir::EvaluateNode const*)+0x86) [0x7fb555803e7a]
  [bt] (5) /home/rhlai/lrh-tensorir/build/libtvm.so(tvm::OpAttrMap<tvm::tir::PrimFunc> tvm::Op::GetAttrMap<tvm::tir::PrimFunc>(tvm::runtime::String const&)+0x2b) [0x7fb555804747]
  [bt] (4) /home/rhlai/lrh-tensorir/build/libtvm.so(tvm::Op::GetAttrMapContainer(tvm::runtime::String const&)+0x27) [0x7fb554fa7bcb]
  [bt] (3) /home/rhlai/lrh-tensorir/build/libtvm.so(tvm::AttrRegistry<tvm::OpRegEntry, tvm::Op>::GetAttrMap(tvm::runtime::String const&)+0xdd) [0x7fb554fb8233]
  [bt] (2) /home/rhlai/lrh-tensorir/build/libtvm.so(tvm::runtime::detail::LogFatal::~LogFatal()+0x36) [0x7fb554bc9d5a]
  [bt] (1) /home/rhlai/lrh-tensorir/build/libtvm.so(tvm::runtime::detail::LogFatal::Entry::Finalize()+0x4a) [0x7fb554bc9ece]
  [bt] (0) /home/rhlai/lrh-tensorir/build/libtvm.so(tvm::runtime::Backtrace[abi:cxx11]()+0x35) [0x7fb55642c9c5]
  File "/home/rhlai/lrh-tensorir/src/ir/../node/attr_registry.h", line 146
TVMError: Attribute 'LowerLogicalIntrin' is not registered

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vinx13 commented Sep 16, 2021

Fixed in #475

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